Vertical Memory Gate Line Positioning via Dummy Reference Features
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Solution Overview
Problem
There is a demand for increasing the integration density of nonvolatile semiconductor memory devices, which is not adequately addressed by traditional two-dimensional transistor structures, necessitating a shift to vertical transistor structures to accommodate smaller and more data-intensive electronic products.
Innovation Solution
A vertical nonvolatile memory device is designed with a substrate featuring a dummy structure and vertically stacked conductive gate lines with insulating layers, where the dummy structure serves as a reference for patterning and includes features like trenches and indentations to facilitate accurate positioning and connection of gate lines, enabling the formation of memory cell strings with stepped terminations and contact plugs for connection to peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional two-dimensional transistor structures are used, then manufacturing processes are simpler, but integration density cannot be sufficiently increased
Solution Approach 1:
The patent transitions from traditional two-dimensional planar transistor structures to three-dimensional vertical transistor structures. The vertical channel extends in the depth direction (z-axis) perpendicular to the substrate surface, with gate lines stacked vertically around the channel. This dimensional change enables significantly higher integration density by utilizing the third dimension for device stacking and three-dimensional memory cell array formation.
2Quantity of substance
If vertical transistor structures are implemented to increase integration density, then more data can be stored, but positioning and connection precision of gate lines becomes more difficult
Solution Approach 1:
The patent introduces dummy structures (dummy trenches, dummy gates, dummy bit lines) formed in advance before the actual gate lines and memory cell structures. These dummy structures serve as reference markers and alignment guides during subsequent patterning and etching processes, enabling precise positioning of vertical channels and gate lines in the three-dimensional structure.
Solution Approach 2:
The dummy structures act as intermediary reference elements that mediate between the substrate and the actual memory cell structures. They provide physical reference points for alignment and positioning, facilitating accurate formation of vertical channels and gate lines without directly participating in the memory function.
3Quantity of substance
If vertically stacked conductive gate lines are formed, then integration density improves, but connection to peripheral circuits becomes more complex
Solution Approach 1:
The patent divides the device into distinct functional regions: a cell array region containing vertical memory cells, and a connection region containing peripheral circuits. Dummy structures are strategically placed at boundaries between these regions to facilitate controlled connections. The segmented approach allows independent optimization of memory cell density and connection architecture.
Solution Approach 2:
Dummy structures positioned at the boundary between cell array and connection regions serve as intermediary elements for signal and power connections. They provide reference points and alignment features that enable precise formation of contact holes and wiring connections between the vertically stacked gate lines in the memory region and the peripheral circuits in the connection region.
Data Source
AI summary
A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.