Vertical Memory Gate Electrode Thickness Control
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Solution Overview
Problem
The challenge is to enhance the integration and reliability of memory devices in electronic products, particularly by improving the manufacturing efficiency and reducing costs of vertical-type memory devices with a vertical transistor structure.
Innovation Solution
The proposed solution involves a vertical-type memory device design that includes a channel layer extending vertically on a substrate, a ground selection transistor with a first replacement gate electrode and etch control layer, and a memory cell with a second replacement gate electrode, allowing for simplified manufacturing processes and reduced costs by eliminating the need for a silicon epi-layer and enabling simultaneous formation of gate electrodes with adjusted thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical transistor structure is used to increase integration degree, then the integration capacity is improved, but the manufacturing complexity increases
Solution Approach 1:
The gate electrode formation process is segmented into two distinct stages: first forming the ground selection transistor gate electrode, then forming the memory cell gate electrode. This segmentation allows each gate electrode to be optimized independently with different thicknesses, simplifying the overall manufacturing process while maintaining high integration capacity.
Solution Approach 2:
The ground selection transistor gate electrode is formed in advance before the memory cell gate electrode. This preliminary action enables subsequent etching processes to selectively remove the first gate electrode without affecting the second gate electrode, reducing manufacturing complexity while preserving vertical structure integration benefits.
2Reliability
If replacement gate electrodes are formed at different heights, then the operational characteristics are improved, but the manufacturing precision requirements increase
Solution Approach 1:
Different regions of the device have different gate electrode thicknesses: the ground selection transistor region has a thicker first gate electrode, while the memory cell region has a thinner second gate electrode. This local quality differentiation is achieved through selective etching processes that remove material only from specific regions, improving operational characteristics without requiring ultra-precise height control across the entire wafer.
Solution Approach 2:
The gate electrode thickness parameter is changed locally through selective removal processes. By controlling etching conditions and using protective layers, the patent achieves different final thicknesses for different gate electrodes, improving device operation while maintaining reasonable manufacturing precision requirements.
3Adaptability or versatility
If the first gate electrode is removed after forming both gates, then the structural flexibility is improved, but the manufacturing time increases
Solution Approach 1:
The ground selection transistor gate electrode is formed and then selectively removed in an intermediate step before the memory cell gate electrode is formed. This preliminary removal action enables the subsequent formation process to create the final gate structure directly, achieving structural flexibility while actually reducing total manufacturing time compared to forming both gates and then removing one.
Solution Approach 2:
The first gate electrode is extracted (removed) from the structure at an optimal point in the manufacturing sequence. This extraction is performed using selective etching that targets only the first gate electrode material or structure, allowing the second gate electrode to be formed subsequently without interference, thus optimizing both structural flexibility and manufacturing efficiency.
Data Source
AI summary
A vertical-type memory device may include a channel layer vertically extending on a substrate, a ground selection transistor at a side of the channel layer on the substrate, the ground selection transistor including a first gate insulation portion and a first replacement gate electrode, an etch control layer on the first replacement gate electrode, and a memory cell on the etch control layer, the memory cell including a second gate insulation portion and a second replacement gate electrode. The etch control layer may include a polysilicon layer doped with carbon, N-type impurities, or P-type impurities, or may include a polysilicon oxide layer comprising carbon, N-type impurities, or P-type impurities. A thickness of the first replacement gate electrode may be the same as a thickness of the second replacement gate electrode, or the first replacement gate electrode may be thicker than the second.