Vertical Memory Gate Structure Warpage Reduction
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Solution Overview
Problem
As the degree of integration in vertical memory devices increases, the mechanical stability and electrical properties of these devices are compromised due to the high number of stacked gate lines and insulation layers, leading to issues with warpage and resistance.
Innovation Solution
The vertical memory device incorporates a stacked structure of non-metal and metal gate patterns with insulating interlayers, where the non-metal gate patterns are made of polysilicon and the metal gate patterns are made of metal or metal silicide, with the metal gate patterns forming a step portion and being selectively positioned around the non-metal gate patterns to reduce the overall metal volume and enhance stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the stacked number of gate lines and insulation layers is increased to achieve higher integration, then the degree of integration is improved, but mechanical stability deteriorates due to warpage
Solution Approach 1:
The patent employs a composite gate line structure consisting of alternating metal gate patterns (high conductivity) and non-metal gate patterns (polysilicon). This composite approach allows the metal portions to provide electrical conductivity while the non-metal portions act as stress-compensating elements that reduce warpage, thereby maintaining mechanical stability during high-temperature processing while achieving high integration through multiple stacked gate lines.
2Productivity
If the stacked number of gate lines is increased to achieve higher integration, then the degree of integration is improved, but electrical properties deteriorate due to increased resistance
Solution Approach 1:
The patent applies local quality by creating gate lines with spatially varying material properties: metal gate patterns are positioned in regions requiring high electrical conductivity (such as word lines and bit lines), while non-metal polysilicon gate patterns are positioned in regions where stress control is more critical. This localized material assignment optimizes both electrical performance and mechanical stability across the device structure.
3Reliability
If more metal gate patterns are used to improve electrical conductivity, then electrical resistance is reduced, but mechanical stability deteriorates due to increased warpage
Solution Approach 1:
The patent segments each gate line into multiple discrete gate patterns with alternating metal and non-metal materials. This segmentation allows the gate line to function as a composite structure where metal segments provide conductivity and non-metal segments provide stress compensation. The segmented approach enables the gate line to achieve both low resistance and reduced warpage compared to using continuous metal gates.
Data Source
AI summary
A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.