Vertical Memory Gate Wiring Layout for Electrical Reliability
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Solution Overview
Problem
As the degree of integration of vertical memory devices increases, the structural and operational reliability is affected due to the increased number of gate lines and insulation layers stacked vertically, leading to issues with electrical reliability.
Innovation Solution
A vertical memory device design where gate lines are arranged and spaced vertically and laterally, with common wirings electrically connected to gate lines at the same level and signal wirings connected via these common wirings, distributed at different levels, and bit lines connected to channels, improving electrical connectivity and reducing cross-talk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of gate lines and insulation layers is increased to achieve higher degree of integration, then storage capacity is improved, but electrical reliability deteriorates due to increased complexity and potential for defects
Solution Approach 1:
The patent transitions from planar 2D gate line arrangements to a 3D vertical stacking configuration. Multiple gate lines are stacked in the vertical direction above channels, enabling higher integration density while maintaining controlled wiring paths. This dimensional change allows more storage capacity without proportionally increasing wiring complexity in the lateral plane.
Solution Approach 2:
The patent segments the wiring system into distinct functional layers: common wirings connected to multiple gate lines at the same level, and signal wirings connected to individual gate lines. This segmentation separates control functions from data functions, reducing cross-talk and improving electrical reliability even as the number of gate lines increases.
2Area of stationary object
If more gate lines are stacked vertically to increase integration density, then area utilization is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent implements a nested structure where gate lines are stacked vertically in defined layers above channels, with each gate line positioned at a specific height. This nested vertical arrangement maximizes area utilization by stacking functionality rather than spreading it laterally, while the defined layer structure provides manufacturing reference planes that help maintain alignment precision.
3Volume of moving object
If gate lines are arranged closely to reduce device footprint, then compactness is improved, but cross-talk between adjacent gate lines increases
Solution Approach 1:
The patent introduces common wirings as intermediary elements that connect to multiple gate lines at the same vertical level. By using these common wirings as mediators, signal distribution is achieved without requiring direct lateral connections between closely spaced gate lines, thereby reducing cross-talk while maintaining compact device footprint.
Data Source
AI summary
A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.