Vertical Memory Stack Layout for GIDL Erase Efficiency
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Solution Overview
Problem
The increasing demands for high performance, high speed, and multifunctionality in semiconductor devices require advanced integration methods, particularly in vertical gate structures to enhance electrical characteristics and data storage efficiency.
Innovation Solution
A semiconductor device design featuring a vertical memory structure with a core region, channel layer, data storage structure, and pad pattern, where gate layers and interlayer insulating layers are alternately stacked, utilizing a specific configuration of dielectric and data storage layers to improve erasing operations through the GIDL phenomenon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate layers and interlayer insulating layers are alternately stacked in vertical direction, then device integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar gate disposition to three-dimensional vertical stacking of gate layers and interlayer insulating layers. This dimensional change enables higher integration density by utilizing the vertical space above the substrate, allowing multiple gate layers to be stacked in the vertical direction while maintaining compact footprint on the substrate plane.
Solution Approach 2:
The gate structure is segmented into multiple discrete gate layers (first gate layer, second gate layer, third gate layer) separated by interlayer insulating layers. This segmentation allows independent formation and control of each gate layer, facilitating modular manufacturing processes while achieving high integration density through vertical stacking.
2Reliability
If data storage structure is positioned between channel layer and gate layers, then electrical characteristics are improved, but device structure complexity increases
Solution Approach 1:
The data storage structure serves as an intermediary layer positioned between the channel layer and the gate layers. This intermediate positioning enables the data storage structure to interact with both the channel layer (for charge storage) and the gate layers (for control), improving electrical characteristics by facilitating efficient charge injection and retrieval while maintaining a systematic layered architecture.
Solution Approach 2:
The data storage structure is specifically positioned at the local region where the channel layer interfaces with the gate layers, creating a localized functional zone for data storage. This local quality enhancement focuses the storage function at the critical interface region, improving electrical characteristics without requiring complex structures throughout the entire device.
3Productivity
If vertical memory structure penetrates through stack structure, then data storage efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The memory structure is configured to extend in the vertical direction, penetrating through the stacked gate layers and interlayer insulating layers. This vertical extension enables the memory structure to access multiple storage regions across different layers, improving data storage efficiency by utilizing the three-dimensional space rather than being confined to a single plane.
Solution Approach 2:
The memory structure is divided into multiple segments corresponding to different vertical levels (first memory structure, second memory structure, third memory structure) that penetrate through different combinations of gate layers and interlayer insulating layers. This segmentation allows independent formation and control of each memory segment, reducing the overall manufacturing precision requirements compared to forming a single continuous structure through all layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances electrical characteristics and data storage efficiency by optimizing the erasing process and improving the efficiency of the GIDL phenomenon, leading to improved semiconductor device performance.
Implementation Method 1
utilizing a specific configuration of dielectric and data storage layers to improve erasing operations through the GIDL phenomenon
Data Source
AI summary
A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.