Vertical Memory Device Reducing Ground Selection Line Resistance
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Solution Overview
Problem
Existing vertical structure non-volatile memory devices face challenges in reducing the resistance of the ground selection line (GSL) electrode and preventing the gate dielectric layer from protruding towards the substrate, which affects integration and reliability.
Innovation Solution
A method involving the formation of a polysilicon sacrificial layer, alternately stacking insulating and sacrificial layers with different etch selectivities, and using a halogen-containing reaction gas for plasma-less thermal etching to create a metallic gate electrode, ensuring the gate dielectric layer forms a uniform plane with the substrate and reducing GSL resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional ground selection line electrode structure is used, then the device structure is simple, but the resistance of the GSL electrode is high
Solution Approach 1:
The ground selection line electrode is formed by nesting multiple conductive layers (first conductive layer, second conductive layer, and third conductive layer) within a single electrode structure. The first conductive layer is positioned at the bottom, followed by the second conductive layer, and the third conductive layer at the top, creating a nested configuration that reduces overall resistance while maintaining structural organization
Solution Approach 2:
The ground selection line electrode utilizes composite material construction by combining multiple conductive layers with different properties. Each conductive layer may have different material compositions and resistance characteristics, and their combination creates a composite electrode structure that achieves lower overall resistance than any single layer could provide
2Manufacturing precision
If the gate dielectric layer is formed without control measures, then the manufacturing process is simple, but the gate dielectric layer protrudes toward the substrate
Solution Approach 1:
A buffer layer is formed on the substrate before forming the gate dielectric layer. This preliminary action creates a controlled interface that prevents the gate dielectric layer from directly contacting and protruding toward the substrate, ensuring proper positioning and spacing is established before the main dielectric layer is deposited
Solution Approach 2:
The buffer layer acts as an intermediary element between the substrate and the gate dielectric layer. This intermediate layer provides a controlled transition zone that prevents direct interaction between the gate dielectric and substrate, thereby preventing protrusion while maintaining manufacturing feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the integration and reliability of the vertical structure non-volatile memory device by reducing the resistance of the GSL electrode and preventing gate dielectric protrusion, leading to improved operating characteristics.
Implementation Method 1
The first sacrificial layer may be removed by performing a plasma-less thermal etch process. The plasma-less thermal etch process may be performed at a temperature lower than 500° C.
Implementation Method 2
The first sacrificial layer may be removed using a halogen-containing reaction gas. The halogen-containing reaction gas may include one gas selected from the group consisting of Cl2, NF3, CIF3, and F2 gases.
Data Source
AI summary
A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer.