Vertical Memory Devices With Identification Patterns
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Solution Overview
Problem
As the integration of vertical memory devices increases, the complexity of these devices intensifies due to the higher number of gate lines and channel blocks, leading to challenges in process and operation reliability.
Innovation Solution
A vertical memory device design that includes a substrate with vertically extending channels, stacked gate lines, and identification patterns at specific levels, along with wirings and dummy wirings, to enhance process and operation reliability through improved address identification and failure detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of the vertical memory device is increased, then the storage capacity is improved, but the complexity of the device is intensified
Solution Approach 1:
The vertical memory device is divided into multiple cell blocks, each with its own unique identification pattern. This segmentation allows the device to maintain high integration while managing complexity through modular organization, where each block can be independently identified and controlled.
Solution Approach 2:
The patent introduces identification patterns that extend the addressing capability into an additional dimensional space. By placing identification patterns at specific locations (such as at the same level as wirings or at different vertical levels), the device can uniquely identify cell blocks without increasing the number of traditional address lines, thus improving storage capacity without proportionally increasing complexity.
2Quantity of substance
If the number of gate lines and cell blocks is increased, then the storage capacity is improved, but the reliability of the device deteriorates
Solution Approach 1:
The identification patterns serve as a feedback mechanism for verifying the correct selection and operation of cell blocks. By providing unique identifiers that can be read and verified, the system can detect and correct addressing errors, thereby maintaining reliability even as the number of gate lines and cell blocks increases.
Solution Approach 2:
The patent replaces traditional mechanical/electrical addressing mechanisms with optical or electromagnetic identification patterns. This substitution allows for more reliable and error-resistant identification of cell blocks, as the patterns can be designed with error-detection capabilities and can be read without physical contact or complex wiring.
3Reliability
If identification patterns are added for address identification, then the reliability is improved, but the device complexity is intensified
Solution Approach 1:
The identification patterns are merged with the existing wiring structure and cell block organization. By integrating the identification patterns into the same fabrication layers and using the same material systems, the patent adds identification capability without creating entirely separate structural systems, thus limiting the increase in device complexity.
Solution Approach 2:
The identification patterns serve multiple functions: they provide unique addresses for cell blocks, enable verification of correct block selection, and can be used for defect detection. This multi-functionality means that a single structural addition achieves multiple reliability improvements without requiring separate systems for each function.
Data Source
AI summary
A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the rings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.