Vertical Memory Channel Structure Using Alternating IGZO Oxides
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Solution Overview
Problem
The integration density of two-dimensional semiconductor memory devices is limited, hindering their ability to meet high performance and low cost demands, as existing micro-pattern formation schemes are inefficient in increasing density without significant technological advancements.
Innovation Solution
A semiconductor memory device with a vertical channel transistor structure, featuring channel structures with alternating metal oxide patterns, including amorphous and c-axis aligned crystalline IGZO, and gallium-rich and indium-rich IGZO, which are strategically positioned and connected to bit-lines and word-lines to enhance integration density and electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional micro-pattern formation schemes are used, then manufacturing process is simple, but integration density is limited
Solution Approach 1:
The channel structure is segmented into multiple distinct metal oxide layers (first metal oxide layer, second metal oxide layer, third metal oxide layer) with different compositions and functions. Each layer is patterned separately to form the vertical channel structure, allowing complex functionality to be achieved through systematic segmentation of the channel formation process.
Solution Approach 2:
The patent transitions from two-dimensional planar channel structures to three-dimensional vertical channel structures. The channel extends vertically through multiple metal oxide layers stacked in the thickness direction, utilizing the third dimension to increase integration density without expanding the planar footprint.
2Manufacturing precision
If vertical channel transistor structure with multiple metal oxide layers is used, then integration density is improved, but manufacturing process complexity increases
Solution Approach 1:
Different metal oxide layers are formed by changing material composition parameters (In-Ga-Zn ratios) and deposition conditions (temperature, pressure) during the manufacturing process. The first metal oxide layer uses one set of parameters while the second and third layers use different parameters, allowing distinct electrical properties to be achieved through controlled parameter variations.
Solution Approach 2:
The channel structure employs composite materials consisting of multiple metal oxide layers with different compositions (In-Ga-Zn-O with varying ratios). Each metal oxide layer is a composite material with specific elemental ratios designed to provide different electrical characteristics, creating a multi-layer composite channel structure that optimizes both density and manufacturability.
3Reliability
If alternating metal oxide patterns with different compositions are used, then electrical properties are enhanced, but material composition control difficulty increases
Solution Approach 1:
Each metal oxide layer is assigned a specific local quality with distinct In-Ga-Zn composition ratios tailored to its functional requirements. The first metal oxide layer has one composition ratio optimized for its electrical role, while the second and third layers have different ratios optimized for their respective roles, achieving superior electrical properties through localized composition optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed device achieves improved integration density and electrical properties, enabling higher performance and potentially lower costs by optimizing the arrangement and composition of metal oxide patterns within the vertical channel transistor structure.
Implementation Method 1
channel structures with alternating metal oxide patterns, including amorphous and c-axis aligned crystalline IGZO
Implementation Method 2
gallium-rich and indium-rich IGZO, which are strategically positioned and connected to bit-lines and word-lines to enhance integration density and electrical properties
Data Source
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AI summary
A semiconductor memory device includes a substrate; a bit-line on the substrate and extending in a first direction; first and second channel patterns on the bit-line; the second channel pattern being spaced apart from the first channel pattern in the first direction; a first word-line between the first and second channel patterns and extending in a second direction that intersects the first direction; a second word-line between the first and second channel patterns, extending in the second direction, and being spaced apart from the first word-line in the first direction; capacitors on and connected to the channel patterns; wherein the first and second channel patterns include first and second metal oxide patterns sequentially on the bit-line, each of the first and second metal oxide patterns include an amorphous metal oxide, and a composition of the first metal oxide pattern is different from a composition of the second metal oxide pattern.