Vertical Memory Device Impurity Region Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing vertical memory devices face challenges in achieving uniform electric characteristics for high integration of semiconductor elements, particularly in ensuring consistent performance across stacked transistors.
Innovation Solution
The memory device incorporates a specific impurity region structure with varying impurity concentrations and types, including first, second, third, and fourth impurity regions, formed through ion implantation and selective epitaxial growth processes, to create vertical and horizontal channel regions, which are connected in series to reduce characteristic distribution and enhance on-currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical stacking of transistors is implemented for high integration, then device density is improved, but uniformity of electric characteristics deteriorates
Solution Approach 1:
The patent applies local quality by creating different impurity concentration zones at specific locations within the vertical transistor structure. First impurity regions are formed at lower portions with higher concentration, while fourth impurity regions are formed at upper portions with lower concentration. This spatial variation in impurity concentration optimizes electric characteristics at different vertical positions, resolving the uniformity issue while maintaining high device density through vertical stacking.
Solution Approach 2:
The patent changes the impurity concentration parameter vertically through the substrate depth. By forming impurity regions with different concentrations (first concentration in lower regions, second concentration in upper regions) and different conductivity types, the patent optimizes the electric characteristics of stacked transistors. This parameter variation compensates for the non-uniform electric fields in vertical structures, achieving uniformity across multiple stacked devices.
2Manufacturing precision
If multiple impurity regions with varying concentrations are formed, then uniformity of electric characteristics is improved, but device complexity increases
Solution Approach 1:
The patent segments the impurity distribution into distinct regions: first impurity regions at lower portions, second impurity regions at upper portions, and fourth impurity regions between them. Each segment serves a specific function in optimizing transistor characteristics. This segmentation allows precise control of electric fields in different vertical zones, achieving uniformity across stacked transistors while organizing the complexity into manageable, functionally-defined segments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure ensures reduced characteristic distribution and increased on-currents across memory cells, improving the uniformity and performance of vertical memory devices by managing impurity concentrations and types strategically.
Implementation Method 1
formed through ion implantation and selective epitaxial growth processes
Implementation Method 2
formed through ion implantation and selective epitaxial growth processes
Data Source
AI summary
A memory device may include a plurality of semiconductor patterns on a substrate including a plurality of first impurity regions doped at a first impurity concentration, a plurality of second impurity regions at portions of the substrate contacting the plurality of semiconductor patterns and doped at a second impurity concentration, a plurality of channel patterns on the plurality of semiconductor patterns, a plurality of gate structures, a plurality of third impurity regions at portions of the substrate adjacent to end portions of the plurality of gate structures, and a plurality of fourth impurity regions at portions of the substrate between the second and third impurity regions and between adjacent second impurity regions. The plurality of fourth impurity regions may be doped at a third impurity concentration which may be lower than the first and second impurity concentrations.