Vertical Memory Device Insulating Interlayer Patterns
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Solution Overview
Problem
Reducing layer thickness in vertical memory devices to increase integration can deteriorate memory device characteristics due to coupling between neighboring memory cells, leading to performance issues.
Innovation Solution
A vertical memory device design featuring insulating interlayer patterns, gate electrodes, and a charge storage pattern structure with tunnel insulation, charge trapping, and blocking patterns, where charge trapping patterns are strategically positioned to minimize parasitic capacitance and maintain device performance, along with a manufacturing method involving alternately formed insulating and sacrificial layers to create recesses and pattern structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If layer thickness is reduced to increase integration, then integration density is improved, but coupling between neighboring memory cells increases causing performance deterioration
Solution Approach 1:
The patent divides the continuous insulating interlayer into segmented insulating interlayer patterns spaced apart from each other. This segmentation creates isolated regions that prevent coupling between neighboring memory cells while maintaining high integration density through the vertical stacking architecture.
Solution Approach 2:
The insulating interlayer patterns serve as intermediary structures between neighboring memory cells. By positioning these insulating patterns at specific locations, the patent mediates the interaction between adjacent cells, blocking parasitic coupling paths while allowing the memory device to maintain high integration through reduced layer thickness.
2Area of stationary object
If charge trapping patterns are positioned close to gate electrodes to reduce area, then device area is reduced, but parasitic capacitance increases affecting performance
Solution Approach 1:
The patent applies local quality by making the charge trapping patterns have different spatial characteristics in different directions. The patterns extend in the first direction (vertical) along gate electrode sidewalls but are spaced apart in the second direction (horizontal), creating an asymmetric distribution that minimizes parasitic capacitance while maintaining compact area.
Solution Approach 2:
The patent resolves the area-capacitance tradeoff by transitioning from a two-dimensional planar arrangement to a three-dimensional vertical arrangement. Charge trapping patterns extend vertically along the sidewalls of gate electrodes and insulating interlayer patterns, utilizing the vertical dimension to reduce horizontal footprint while maintaining sufficient spacing to minimize parasitic capacitance.
Data Source
AI summary
A vertical memory device includes insulating interlayer patterns, of gate electrodes, a channel, and a charge storage pattern structure. The insulating interlayer patterns are spaced in a first direction. The gate electrodes between are neighboring insulating interlayer patterns, respectively. The channel extends through the insulating interlayer patterns and the gate electrodes in the first direction. The charge storage pattern structure includes a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked between the channel and each of the gate electrodes in a second direction. The charge trapping pattern structure includes charge trapping patterns spaced in the first direction. The charge trapping patterns are adjacent to sidewalls of first gate electrodes, respectively. A first charge trapping pattern extends in the first direction along a sidewall of a first insulating interlayer pattern.