Vertical Memory Devices With Inter-Structure Layers
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Solution Overview
Problem
Current vertical memory devices face challenges in achieving high integration and reliability while maintaining manufacturing efficiency.
Innovation Solution
The design incorporates a vertical memory device structure with stacked gate electrodes and insulation film patterns alternately stacked on a substrate, featuring an inter-structure layer and a channel structure that penetrates through the stacked structures, connected to the substrate, allowing for improved integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically to increase integration, then storage capacity increases, but manufacturing complexity and reliability challenges increase
Solution Approach 1:
The vertical memory structure is divided into multiple stacked structures, each containing gate electrodes and insulation film patterns alternately stacked. This segmentation allows for modular manufacturing and assembly, reducing overall manufacturing complexity while maintaining high storage capacity.
Solution Approach 2:
The patent transitions from planar memory architecture to vertical stacking, utilizing the third dimension (height) to increase storage capacity. Multiple gate electrodes and insulation layers are stacked vertically, enabling higher integration without proportionally increasing manufacturing complexity.
2Quantity of substance
If more stacked structures are added to increase integration, then storage capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
Inter-structure layers are positioned between adjacent stacked structures before final assembly, serving as pre-positioned alignment references. This preliminary action establishes precise spatial relationships between stacked structures, reducing the precision requirements during subsequent manufacturing steps.
Solution Approach 2:
The inter-structure layer acts as an intermediary element between stacked structures, providing a reference plane and spacing mechanism. This intermediary component simplifies the alignment process and reduces the direct precision requirements between gate electrode stacks.
3Reliability
If channel structure penetrates through all stacked structures, then electrical connectivity is improved, but structural reliability challenges increase
Solution Approach 1:
The channel structure extends vertically through all stacked structures in the third dimension, establishing direct electrical pathways from the substrate through multiple insulation and gate layers. This vertical connectivity approach improves electrical reliability without requiring complex lateral routing.
Solution Approach 2:
The channel structure serves multiple functions simultaneously: it provides electrical connectivity, acts as a structural support element, and defines the spatial arrangement of gate electrodes. This multi-functionality reduces the need for additional separate components, simplifying overall structural complexity.
Data Source
AI summary
A vertical memory device includes a plurality of stacked structures, at least one inter-structure layer, and a channel structure. The plurality of stacked structures comprises a plurality of gate electrodes and a plurality of insulation film patterns that are alternately and repeatedly stacked on a substrate. At least one inter-structure layer is positioned between the two stacked structures adjacent to each other from among the plurality of stacked structures. A channel structure penetrates the plurality of stacked structures and the at least one inter-structure layer, the channel structure extending in the first direction, the channel structure being connected to the substrate.