Vertical 1T Memory Staircase Structure for Lower Leakage
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to process complexity and cost as feature sizes approach a lower limit, and capacitor-less one transistor memory structures suffer from word line pillar capacitive coupling, impacting device performance.
Innovation Solution
A vertical memory structure with a capacitor-less multi-gate 1T memory design, featuring a pillar surrounded by a word line gate, a plate line gate, and a bottom selection gate, which includes a staircase structure to reduce leakage current and improve data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to vertical (3D) memory architecture. The vertical channel extends in the vertical direction rather than laterally, enabling higher memory density without proportionally increasing process complexity. The staircase structure with multiple tiers arranged vertically allows compact stacking of memory cells, achieving high density through spatial reconfiguration rather than continuous lateral scaling.
Solution Approach 2:
The vertical channel is segmented into multiple tiers (first tier, second tier, third tier) with distinct functional regions. Each tier contains segmented control gates (first control gate, second control gate, third control gate) that can be independently controlled. This segmentation allows for sophisticated memory operations and reduces interference between adjacent memory elements, managing device complexity through modular functional division.
2Quantity of substance
If feature sizes of memory cells approach a lower limit, then memory density is improved, but fabrication difficulty and cost increase
Solution Approach 1:
By moving to vertical architecture, the patent achieves high memory density using larger effective feature sizes in the lateral direction. The vertical channel length extends in the Z-direction rather than requiring smaller lateral dimensions, allowing fabrication processes to operate at more manageable scale levels while still achieving high density through vertical stacking.
Solution Approach 2:
The staircase structure implements a nested arrangement where multiple memory cell tiers are stacked vertically within a compact footprint. The first tier, second tier, and third tier are nested in the vertical direction, with each tier containing nested control gates and channel regions. This nesting achieves high density without requiring proportionally smaller fabrication features.
3Device complexity
If capacitor-less one transistor memory structures are used, then device simplicity is improved, but word line pillar capacitive coupling increases
Solution Approach 1:
The control gate structure is segmented into multiple independently controllable gates (first control gate, second control gate, third control gate) positioned at different vertical levels. This segmentation allows for independent voltage control of each gate region, enabling precise control of charge injection and retrieval operations. The segmented structure reduces unwanted capacitive coupling by providing electrical isolation between different control regions through the dielectric layers.
Solution Approach 2:
Dielectric layers are introduced as intermediary materials between the control gates and the vertical channel, and between adjacent control gates. These dielectric intermediaries reduce direct capacitive coupling while still allowing electric field penetration for charge control. The dielectric layers act as mediators that enable electrical control while minimizing parasitic capacitance effects.
Data Source
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AI summary
The present disclosure is directed to a memory structure including a staircase structure. The staircase structure can include a bottom select gate, a plate line formed above the bottom select gate, and a word line formed above the plate line. The pillar can extend through the bottom select gate, the plate line, and the word line. The memory structure can also include a source structure formed under the pillar and a drain cap formed above the pillar. The memory structure can further include a bit line formed above the drain cap.