Vertical Memory Device Logic Circuit Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face challenges in increasing integration density while minimizing layout area, leading to issues with wiring line lengths and RC delays, which affect performance and fabrication costs.
Innovation Solution
A memory device with a vertical structure is designed, featuring a cell wafer with a memory cell array and peripheral wafers containing logic circuits, where the page buffer low-voltage circuit is in one wafer and the row decoder and page buffer high-voltage circuits are in another, optimizing the placement of transistors and dielectric layers to reduce wiring complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all logic circuits are disposed in a single peripheral wafer, then device complexity is reduced, but wiring line length increases causing RC delays
Solution Approach 1:
The logic circuit is divided into two separate peripheral wafers: a first peripheral wafer containing the page buffer low-voltage circuit, and a second peripheral wafer containing the page buffer high-voltage circuit, row decoder circuit, and peripheral circuit. This segmentation reduces wiring line lengths within each wafer, thereby minimizing RC delays while maintaining overall device functionality.
2Reliability
If more types of gate dielectric layers are used, then transistor performance is optimized, but fabrication cost increases
Solution Approach 1:
Different peripheral wafers use different numbers of gate dielectric layer types according to their specific functional requirements. The first peripheral wafer uses a first number of gate dielectric layer types, while the second peripheral wafer uses a second number of gate dielectric layer types, which may differ. This local optimization achieves necessary transistor performance while minimizing overall fabrication complexity and cost.
Data Source
AI summary
A memory device having a vertical structure includes a memory cell array defined in a cell wafer, and having a plurality of word lines extending in a first direction and arranged in a second direction, and having a plurality of bit lines extending in the second direction and arranged in the first direction; and a logic circuit configured to control the memory cell array, and including a page buffer low-voltage circuit, a page buffer high-voltage circuit, a row decoder circuit and a peripheral circuit, wherein the page buffer low-voltage circuit is disposed in a first peripheral wafer and the page buffer high-voltage circuit, the row decoder circuit and the peripheral circuit are disposed in a second peripheral wafer, and wherein the cell wafer overlaps with the first peripheral wafer and the second peripheral wafer in a vertical direction that is perpendicular to a plane formed by the first direction and the second direction.