3D Vertical Memory Cell Layout for Dense, Low-Leakage Arrays
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to increased complexity and cost as feature sizes approach limits, and existing transistors complicate the arrangement of interconnect structures, leading to reduced memory cell efficiency and increased leakage current.
Innovation Solution
The implementation of vertical transistors, such as multi-gate and single-gate transistors, which reduce the area occupied by transistors, simplify interconnect structures, and allow bit lines and storage units to be arranged on opposite sides, thereby reducing fabrication complexity and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but fabrication complexity and cost increase as feature sizes approach lower limits
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked architecture. Memory cells are arranged in multiple tiers stacked vertically, with each tier containing memory cells formed over different active regions of the semiconductor substrate. This vertical stacking enables significantly higher memory density without further reducing lateral feature sizes, thereby avoiding the fabrication complexity and cost increases associated with scaling planar cells to smaller dimensions.
2Reliability
If existing transistors are used in memory cells, then transistor functionality is achieved, but interconnect structure arrangement becomes complicated and leakage current increases
Solution Approach 1:
The patent employs vertical transistors where the channel extends in the vertical direction rather than laterally. The gate structure wraps around the channel region vertically, and bit lines are positioned above and below the channel region at different vertical levels. This vertical arrangement simplifies interconnect routing compared to planar transistors, as bit lines can be directly connected to the channel from opposite sides without complex lateral routing, thereby reducing interconnect structure complexity and leakage current.
3Area of moving object
If vertical transistors are implemented, then transistor area is reduced and interconnect structures are simplified, but new fabrication challenges arise
Solution Approach 1:
The patent divides the memory device into multiple tiers stacked vertically, with each tier containing memory cells formed over separate active regions. This segmentation allows independent formation and optimization of each tier's transistor structure. The vertical transistors in each tier can be fabricated using similar processes, enabling modular manufacturing that reduces overall fabrication complexity despite the three-dimensional architecture.
Solution Approach 2:
The patent forms bit lines and bit line contacts in advance before forming the vertical transistors. The bit line contacts are positioned at different vertical levels, and the bit lines are pre-configured to extend above and below the channel region. This preliminary action simplifies subsequent transistor formation, as the interconnect structure is already in place to receive the vertical transistors, thereby easing fabrication processes.
Data Source
AI summary
In certain aspects, a three-dimensional (3D) memory device includes a semiconductor structure including an array of memory cells, a plurality of bit lines coupled to the memory cells, and a plurality of word lines coupled to the memory cells. Each memory cell includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. Each bit line extends in a second direction perpendicular to the first direction. Each word line extends in a third direction perpendicular to the first direction and the second direction. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the third direction and one side of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.