Vertical Memory Device Structure for Low Voltage Operation
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Solution Overview
Problem
Existing horizontal transistors in resistive memory devices face limitations in reducing operation voltage and are prone to word line resistance variations, restricting current drivability and integration density in ultra-high capacity, high-speed memory devices.
Innovation Solution
A vertical memory device structure is developed, featuring a common source region, channel regions, trenches, conductive layers, and a data storage material, with a method of fabrication that includes forming junction regions, channel regions, and conductive layers on a semiconductor substrate, followed by patterning and insulating layer formation to create a line-patterned structure with overlapping conductive layers for improved current drivability and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If horizontal transistors are used in resistive memory devices, then the device structure is simpler to manufacture, but the operation voltage cannot be reduced below 1.1 V and current drivability is limited
Solution Approach 1:
The patent transitions from horizontal transistor structures to vertical transistor structures, changing the spatial dimension of current flow. This vertical configuration enables lower operation voltages (below 1.1 V) while maintaining manufacturability through established semiconductor fabrication processes adapted for vertical geometries.
Solution Approach 2:
The patent employs composite material structures including semiconductor layers (e.g., SiGe, GaAs), insulating materials, and conductive layers in a vertically stacked configuration. This composite approach enables both low operation voltage and adequate current drivability by optimizing material properties at each layer.
2Ease of operation
If diodes are used as access elements, then the device structure is simpler, but the operation voltage must be 1.1 V or more and word line resistance varies causing word line bounce
Solution Approach 1:
The patent replaces planar diode structures with vertical transistor structures, enabling stable low-voltage operation. The vertical configuration with controlled channel regions eliminates word line resistance variations and bounce issues while maintaining structural simplicity through compact stacking.
Solution Approach 2:
The patent introduces locally optimized regions including doped source/drain regions, gate structures, and channel regions with specific electrical properties. This local quality control enables stable operation voltage and eliminates word line bounce by precisely controlling electrical characteristics at each vertical level.
3Productivity
If horizontal transistor structures are used, then the manufacturing process is established, but the integration density and current drivability cannot be sufficiently increased
Solution Approach 1:
The patent implements vertical transistor structures that stack multiple functional layers (source, channel, drain, gate) in the vertical dimension, enabling higher integration density without increasing lateral footprint. This three-dimensional configuration maintains manufacturability while significantly improving current drivability and device capacity.
Data Source
AI summary
A vertical memory device capable of minimizing a cell size and improving current drivability and a method of fabricating the same are provided. The vertical memory device includes a common source region and source regions formed on the common source region and extending in a first direction. Channel regions are formed on each of the source regions, the channel regions extending in the first direction. Trenches are formed between the channel regions. A drain region is formed on each of the channel regions. A conductive layer is formed on a side of each of the channel regions, the conductive layer extending to the first direction. A data storage material is formed on each of the drain regions.