Vertical Memory Transistor Layout for Higher Density and Lower Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Planar memory cells face challenges in scaling due to increased complexity and cost as feature sizes approach a lower limit, limiting memory density and efficiency.
Innovation Solution
Implementing vertical transistors with a semiconductor layer and gate structure, arranged perpendicularly to bit and gate lines, and bonding memory cell arrays with peripheral circuits on different wafers to reduce area and simplify interconnects, using multi-gate transistors for better channel control and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density increases, but fabrication complexity and cost increase significantly as feature sizes approach a lower limit
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to vertical (3D) memory cell architecture. The vertical transistor channel extends in the vertical direction rather than laterally, enabling memory density improvement without proportionally increasing fabrication complexity. This dimensional change allows continued scaling benefits while avoiding the complexity penalties of ultra-fine lateral feature sizes.
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density increases, but manufacturing cost increases due to challenging process requirements
Solution Approach 1:
By moving to vertical transistor architecture, the patent achieves memory density improvement through vertical channel length rather than lateral feature size reduction. This approach uses more conventional fabrication processes at larger lateral dimensions, thereby reducing manufacturing cost while maintaining high memory density.
3Reliability
If vertical transistors are used with multi-gate structures, then channel control improves and leakage current reduces, but device structure becomes more complex
Solution Approach 1:
The patent merges the gate structure to wrap around and contact multiple sides of the vertical semiconductor channel (e.g., three-sided or four-sided gates). This merging of gate contacts to multiple surfaces of the channel provides superior electrostatic control and reduced leakage current, while the vertical architecture itself simplifies the overall device structure compared to achieving similar control in planar devices.
Data Source
AI summary
A semiconductor device and method for forming thereof is provided. The semiconductor device includes vertical transistors, storage units, and a bonding layer. Each vertical transistor includes a semiconductor layer and a gate structure. The semiconductor layer has a leakage value lower than a pico-ampere and extends along a vertical direction. The gate structure is coupled with one side of the semiconductor layer. Each storage unit is coupled with the semiconductor layer of the vertical transistor. The bonding layer is configured to couple the vertical transistors with a peripheral circuit. The vertical transistors are disposed between the bonding layer and the storage units.