Multi-cell vertical memory nodes for density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing NAND memory architectures are limited in physical cell density due to the minimum size constraints of floating gate memory cells, which restrict the reduction of feature sizes and thus the density of memory devices.
Innovation Solution
The implementation of vertically oriented memory nodes with multiple non-volatile memory cells on opposing sides of a channel, each with corresponding control gates, allowing for increased cell density by utilizing advanced etching processes and materials like polysilicon diodes or MiM/MiiM diodes, enabling higher storage capacity without exceeding semiconductor fabrication limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are reduced to increase density, then memory cell density improves, but operational characteristics of floating gate memory cells deteriorate below minimum size limits
Solution Approach 1:
The patent transitions from planar memory cell arrangement to vertical stacking architecture. Multiple memory cells are stacked vertically along a channel, enabling density improvement in the vertical dimension rather than further reducing horizontal feature sizes. This maintains operational characteristics while achieving higher density through three-dimensional cell arrangement.
Solution Approach 2:
The patent segments a single memory node into multiple independent memory cells stacked vertically. Each cell can be independently controlled via control gates, allowing the node to function as multiple storage units. This segmentation increases the number of storage cells per node without compromising individual cell operational characteristics.
2Ease of manufacture
If single physical cell per node architecture is used, then fabrication is simplified, but physical memory cell to memory node ratio is limited
Solution Approach 1:
The patent extends the memory cell arrangement from two-dimensional planar layout to three-dimensional vertical stacking within each memory node. Multiple cells are positioned at different vertical levels along a shared channel, increasing the cell-to-node ratio by utilizing the vertical dimension while maintaining fabrication compatibility with existing processes.
Solution Approach 2:
The patent makes a single memory node serve multiple storage functions by stacking multiple cells within it. The shared channel and control gate structure enable each node to accommodate multiple independently addressable cells, increasing storage capacity per node without requiring proportionally more complex fabrication processes.
3Area of moving object
If channel length and spacing between memory cells are reduced, then area density improves, but minimum size constraints are reached that limit further reduction
Solution Approach 1:
The patent moves the density improvement strategy from reducing channel length in the horizontal plane to extending cell stacking in the vertical direction. The channel maintains its minimum viable length for operational characteristics, while multiple cells are arranged vertically along this channel, achieving area density improvement without further horizontal dimension reduction.
Solution Approach 2:
The patent segments the vertical space above the channel into multiple discrete cell regions, each with its own control gate. This segmentation allows independent operation of each cell while sharing the same channel infrastructure, effectively increasing storage density without requiring further reduction of the channel's horizontal dimensions.
Data Source
AI summary
Embodiments of the invention pertain to vertical memory structures. Embodiments of the invention describe memory nodes comprising two memory cells on opposing sides of a vertical channel separating a source region and a drain region. Embodiments of the invention may utilize floating gate NAND memory cells, polysilicon diodes, MiM diodes, or MiiM diodes. Embodiments of the invention may be used to form flash memory, RRAM, Memristor RAM, Oxide Ram or OTPROM.