Vertical Channel Memory Gate Oxide Doping for Lower Leakage
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Solution Overview
Problem
The challenge of increasing the degree of integration in semiconductor memory devices is limited by the need for ultra-expensive apparatuses to miniaturize patterns, particularly in two-dimensional designs, which restricts cost-effective performance improvements.
Innovation Solution
The introduction of semiconductor memory devices with vertical channel transistors and specific gate metal oxide film configurations, including impurity elements like phosphorus, arsenic, nitrogen, or germanium, to enhance integration and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-dimensional planar semiconductor memory device structure is used, then manufacturing process is simpler, but degree of integration is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical structure by extending the channel region vertically. The channel region extends from the first main surface to the second main surface of the substrate, creating a vertical channel transistor that increases the number of memory cells per unit area without requiring more complex manufacturing processes
2Quantity of substance
If pattern miniaturization is pursued to increase integration, then degree of integration improves, but manufacturing cost increases due to ultra-expensive apparatuses
Solution Approach 1:
Instead of miniaturizing patterns in two dimensions which requires expensive equipment, the patent extends the channel region in the vertical direction (third direction perpendicular to first and second directions). This vertical extension allows increased integration using existing manufacturing capabilities without requiring ultra-expensive pattern miniaturization apparatuses
3Reliability
If gate metal oxide film with impurity element is used, then leakage current is reduced, but manufacturing process becomes more complex
Solution Approach 1:
The patent introduces an impurity element into only a specific portion of the gate metal oxide film (the portion overlapping the channel region), rather than the entire gate structure. This localized doping approach reduces leakage current in the critical area while maintaining simpler manufacturing compared to comprehensive gate structure modifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the degree of integration and reduces leakage current, enabling higher performance and lower costs by optimizing the vertical channel transistor structure.
Implementation Method 1
the gate metal oxide film includes a first portion and a second portion, the first portion of the gate metal oxide film overlapping the first portion of the word line in a third direction, the second portion of the gate metal oxide film overlapping the second portion of the word line in the third direction, the first portion of the gate metal oxide film includes an impurity element
Data Source
AI summary
A semiconductor memory device includes a channel region, a word line extending in a first direction, the word line including a first portion and a second portion stacked in a second direction perpendicular to the first direction, a gate insulating film between the channel region and the word line, and a gate metal oxide film between the gate insulating film and the word line, the gate metal oxide film including metal oxide, wherein the gate metal oxide film includes a first portion overlapping the first portion of the word line in a third direction and the second portion overlapping the second portion of the word line in the third direction, the first portion of the gate metal oxide film includes an impurity element, the second portion of the gate metal oxide film does not include the impurity element, and the second direction is perpendicular to the third direction.