Vertical Memory Cell Stacks With Partial Doping to Cut Leakage
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to limitations in process technology and fabrication techniques, leading to reduced memory density and increased complexity, with vertical transistors experiencing floating body effects and high leakage currents.
Innovation Solution
Implementing vertical transistors with partially doped semiconductor bodies and interleaved dielectric and conductive layers, allowing for stacked storage units and face-to-face bonding of memory cell arrays and peripheral circuits to reduce area and improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but feature sizes approach a lower limit making planar process and fabrication techniques challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) architecture by stacking multiple memory cell layers vertically. This dimensional change allows continued scaling and density improvement without further reducing lateral feature sizes, thereby avoiding the fabrication challenges and costs associated with extreme planar scaling.
Solution Approach 2:
The memory device is divided into multiple stacked memory cell layers, each containing vertical transistors and storage units. This segmentation allows independent optimization of each layer and enables parallel processing during fabrication, reducing overall fabrication complexity while achieving high density through vertical stacking.
2Quantity of substance
If vertical transistors are implemented in 3D memory architecture, then memory density is improved, but floating body effects and high leakage currents occur
Solution Approach 1:
The semiconductor body of the vertical transistor is partially doped rather than uniformly doped. Specifically, the first portion of the semiconductor body is doped while the second portion remains undoped or lightly doped. This local quality variation reduces floating body effects and leakage currents by creating appropriate potential gradients while maintaining the vertical transistor's high density advantages.
Solution Approach 2:
The doping concentration and distribution in the semiconductor body are modified to optimize transistor performance. By changing the doping parameters (concentration, depth, distribution), the patent suppresses floating body effects and reduces leakage currents while preserving the vertical transistor architecture's density benefits.
3Quantity of substance
If stacked storage units are implemented, then memory density is improved, but fabrication process complexity increases
Solution Approach 1:
Interleaved dielectric layers and conductive layers are formed above the semiconductor body before final transistor completion. This preliminary action simplifies subsequent fabrication steps by pre-establishing the stacked storage unit structure and electrical connections, making the overall manufacturing process more manageable despite the three-dimensional architecture.
Data Source
AI summary
In certain aspects, a memory device includes a first semiconductor structure. The first semiconductor structure includes a vertical transistor including a semiconductor body extending in a first direction, a plurality of storage units stacked in the first direction and coupled to a first end of the vertical transistor, and a plurality of plate lines each extending perpendicularly to the first direction and coupled to a respective one of the storage units.