Vertical Memory Cell Array Pillar Integration
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Solution Overview
Problem
Current resistive memory devices face limitations in integration density due to horizontal transistor structures and high operation voltages required by diodes, which also lead to word line resistance variations and 'word line bouncing' issues.
Innovation Solution
A memory cell array design featuring vertically arranged active pillars with inter-pattern insulating layers and surrounding word lines, allowing for reduced distances between pillars and improved current drivability, while maintaining efficient voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If horizontal transistor structures are used, then current drivability is ensured, but integration density is limited
Solution Approach 1:
The patent transitions from horizontal transistor structures to vertical transistor structures, changing the spatial arrangement from two-dimensional planar layout to three-dimensional vertical stacking. This dimensional change allows multiple active pillars to be arranged vertically above each other, significantly increasing integration density while maintaining current drivability through the vertical channel.
Solution Approach 2:
The patent implements a nested structure where bit lines are formed between active pillars, and word lines surround the active pillars in a nested configuration. The insulating layers are nested between adjacent active pillars, creating a compact three-dimensional arrangement that maximizes space utilization and integration density.
2Use of energy by moving object
If diodes are used as access devices, then device simplicity is maintained, but operation voltage must be 1.1V or more
Solution Approach 1:
The patent changes the electrical parameters of the access device by using transistors instead of diodes. This allows the operation voltage to be reduced from 1.1V or more (required by diodes) to lower voltages suitable for transistor operation, thereby reducing energy consumption while providing better voltage control for memory operations.
3Reliability
If word lines are formed on active pillars, then cell selection is enabled, but word line resistance varies by position causing bouncing
Solution Approach 1:
The patent introduces insulating layers as intermediary elements between adjacent active pillars and between word lines and active pillars. These insulating layers electrically isolate different word lines from each other and from active pillars, preventing current leakage and eliminating word line bouncing issues while maintaining effective cell selection capability.
4Quantity of substance
If active pillars are arranged closely in extension direction of word line, then integration density increases, but distance between pillars in row direction cannot be reduced
Solution Approach 1:
The patent arranges active pillars in a vertical stacking configuration rather than purely horizontal arrangement. This allows active pillars to be positioned closely in the row direction while maintaining adequate spacing through vertical separation, effectively increasing integration density without compromising pillar间距 in critical directions.
Data Source
AI summary
A memory cell array includes a semiconductor substrate, a first word line formed on the semiconductor substrate, a second word line formed on the semiconductor substrate and extending substantially parallel to the first word line, a first inter-pattern insulating layer interposed between the first and second word lines, first active pillars formed within the first word line and arranged along the first word line at a first interval, and second active pillars formed within the second word lines, and arranged along the second word line to face the first active pillars, respectively, with the first inter-pattern insulating layer interposed therebetween.