Vertical Memory Pillar Connection Layout for Higher Storage Density
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Solution Overview
Problem
Current memory devices face challenges in increasing data storage capacity effectively, particularly in vertical type memory devices where connecting pillar structures within memory cell strings is complex and inefficient.
Innovation Solution
The proposed solution involves a vertical type memory device design with specific pillar structures, including a first pillar structure with a variable resistance layer and a connection pad, and a second pillar structure connected to the first pillar structure through a connection pad, facilitating easy connection and alignment within the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pillar structures are connected in vertical type memory devices to increase data storage capacity, then storage capacity is improved, but connection complexity increases
Solution Approach 1:
The memory device is divided into multiple pillar structures (first pillar structure, second pillar structure, third pillar structure) that are vertically stacked and independently formed. Each pillar structure contains memory cell strings with specific configurations (e.g., first memory cell strings in the first pillar structure, second memory cell strings in the second pillar structure). This segmentation allows for modular construction and simplified connection processes while achieving high storage capacity through vertical integration.
Solution Approach 2:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertical pillar structures. Memory cells are arranged in vertical stacks along the channel length direction, with multiple pillar structures positioned at different heights (first pillar structure at first height, second pillar structure at second height, third pillar structure at third height). This dimensional change enables significantly increased storage capacity within the same footprint area.
2Quantity of substance
If pillar structures are vertically stacked to increase storage density, then storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning and formation of pillar structures before final connection. The first pillar structure is formed with predetermined positions and dimensions, followed by formation of the second pillar structure aligned to the first, and then the third pillar structure aligned to both. This sequential preliminary action ensures proper alignment and reduces manufacturing precision requirements by establishing reference structures before subsequent structures are formed.
Solution Approach 2:
Multiple pillar structures are nested vertically within the same lateral footprint area. The first pillar structure, second pillar structure, and third pillar structure are positioned at different heights along the vertical axis, with each pillar structure containing memory cell strings that are nested within the pillar's cylindrical or rectangular boundary. This nesting approach maximizes storage density while maintaining manageable manufacturing complexity.
Data Source
AI summary
A vertical type memory device includes a first pillar structure in a channel hole inside a word line mold, and a second pillar structure in a string select line hole overlapping the channel hole inside a string select line mold. The first pillar structure includes a first gate insulating layer and a cell channel layer on an inner wall of the channel hole, a variable resistance layer on one side of the cell channel layer, a first filling insulating layer filling the channel hole, and a connection pad in an upper portion of the first filling insulating layer. The second pillar structure includes a second gate insulating layer on an inner wall of the string select line hole, a select channel layer on one side of the second gate insulating layer, and a second filling insulating layer filling the string select line hole on the select channel layer.


