Vertical Memory Pillar Architecture for Density and Leakage Control
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Solution Overview
Problem
Planar memory cells face challenges in density limitations and increased costs as feature sizes approach a lower limit, necessitating a more efficient memory architecture.
Innovation Solution
The development of a vertical memory structure with a method that includes specific voltage bias applications to perform programming and erasing operations, utilizing a bottom select gate, plate line, word line, pillar, source line, drain cap, and bit line configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but manufacturing complexity and cost increase significantly as feature sizes approach a lower limit
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to vertical (3D) memory cell architecture. The vertical memory cell extends structures in the vertical dimension with a pillar extending through multiple gate structures stacked vertically, allowing memory density improvement without proportionally increasing manufacturing complexity at the feature size limit.
Solution Approach 2:
The vertical memory cell structure nests multiple functional components within a compact vertical footprint. The pillar is surrounded by multiple gate structures (bottom select gate, plate line, word line, drain cap) that are stacked vertically, with each gate structure containing control electrodes and insulation layers nested within each other, achieving high density without excessive manufacturing steps.
2Quantity of substance
If feature sizes of memory cells are reduced to increase density, then memory capacity is improved, but leakage current increases and data retention deteriorates
Solution Approach 1:
Multiple gate structures (bottom select gate, plate line, word line, drain cap) are nested vertically around the pillar, creating multiple control points for charge storage. This nested configuration allows better control of leakage current through the pillar while maintaining data retention, as each gate structure can independently control electrical characteristics at different vertical levels.
Solution Approach 2:
Different gate structures are positioned at specific vertical locations around the pillar to provide localized control. The bottom select gate controls access at the lower region, the plate line and word line control the middle region, and the drain cap controls the upper region, allowing optimized local electrical characteristics to prevent leakage and maintain data retention throughout the pillar.
3Quantity of substance
If vertical memory architecture is implemented to address density limitations, then memory density is improved, but device structure complexity increases
Solution Approach 1:
The patent implements vertical memory architecture by extending the memory cell structure in the vertical dimension. The pillar extends vertically through stacked gate structures, and all components are arranged vertically rather than laterally, achieving higher density by utilizing the third dimension while maintaining a relatively compact footprint.
Solution Approach 2:
The vertical memory cell is segmented into distinct functional regions: the bottom select gate structure for selection control, the plate line and word line structures for data operation control, and the drain cap structure for charge storage control. Each segment is independently formed and controlled, allowing complex functionality to be achieved through modular vertical segmentation rather than monolithic complex structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data retention and reduces leakage current, improving the performance and efficiency of memory devices by overcoming the limitations of planar memory cells.
Implementation Method 1
applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line
Implementation Method 2
applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias
Implementation Method 3
applying a negative voltage bias to the source line
Data Source
AI summary
A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.