Vertical Memory Cell Pillars With Single-Mask Capacitor Integration
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Solution Overview
Problem
Current methods for forming arrays of memory cells and capacitors in integrated circuitry face challenges in efficiently integrating vertical transistors and capacitors, often requiring multiple masks and critical alignments, which can be time-consuming and prone to errors.
Innovation Solution
The method involves forming a vertical stack with transistor material above a capacitor electrode material, using masks to etch both materials simultaneously to create pillars, and then forming capacitors and transistors above these pillars, reducing the number of critical masks and alignments needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used to form arrays of memory cells and capacitors, then integration of vertical transistors and capacitors is achieved, but multiple masks and critical alignments are required which increases process complexity and time consumption
Solution Approach 1:
The patent combines the formation of transistor gates and capacitor electrodes into a single simultaneous etching process using one mask layer. This merging of operations eliminates the need for separate masking and alignment steps that would otherwise be required for forming these structures independently, thereby simplifying the fabrication process while maintaining precise structural integration.
Solution Approach 2:
The single mask layer serves multiple functions: it defines both the transistor gate regions and the capacitor electrode regions simultaneously. This multi-functional use of the mask eliminates the need for multiple specialized masks, reducing both the number of masking steps and the complexity of critical alignments between different mask layers.
2Reliability
If multiple masks and critical alignments are used, then precise integration is achieved, but process time increases and errors become more probable
Solution Approach 1:
By merging the definition of transistor gates and capacitor electrodes into a single etching operation, the patent eliminates multiple sequential steps that would accumulate time and potential alignment errors. The simultaneous formation ensures precise spatial relationships while reducing total process time and minimizing opportunities for manufacturing variations.
3Manufacturing precision
If multiple masks and critical alignments are required, then precise positioning is achieved, but manufacturing efficiency decreases
Solution Approach 1:
The patent achieves precise positioning of transistor gates and capacitor electrodes relative to each other by defining both structures in a single etching step from one mask layer. This approach maintains the precise spatial relationships required for proper device function while eliminating the cumulative alignment tolerances that would result from multiple sequential masking steps, thereby improving manufacturing efficiency.
Data Source
AI summary
A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars. Other aspects and embodiments are disclosed, including structure independent of method.