3D Vertical Chalcogenide Memory Layout With Late-Stage Plug Integration
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Solution Overview
Problem
Existing memory devices face challenges in efficiently manufacturing 3D vertical chalcogenide memory devices with high integration and performance, particularly in forming vertical data lines and chalcogenide material plugs within alternating stacks of conducting and dielectric layers.
Innovation Solution
A method involving the formation of trenches in an alternating stack of conducting word line layers and dielectric layers, followed by the introduction of vertical data lines and chalcogenide material plugs, utilizing high-K materials for ohmic contacts and preserving chalcogenide material integrity through late-stage integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional manufacturing methods are used to form vertical data lines and chalcogenide material plugs in alternating stacks, then device integration is achieved, but manufacturing efficiency and performance are insufficient
Solution Approach 1:
The method performs preliminary actions by forming trenches and introducing vertical data lines before integrating the chalcogenide material plugs in late-stage processing. This preliminary structuring allows subsequent precise placement of chalcogenide material without compromising the alternating stack architecture, thereby improving manufacturing efficiency while maintaining device performance
Solution Approach 2:
The manufacturing process is segmented into distinct stages: trench formation, vertical data line introduction, and late-stage chalcogenide material plug integration. This segmentation allows each component to be optimized independently, improving overall manufacturing efficiency while ensuring reliable electrical coupling and maintaining chalcogenide material integrity
2Ease of manufacture
If chalcogenide material is introduced early in the manufacturing process, then integration is simplified, but chalcogenide material integrity is compromised
Solution Approach 1:
The alternating stack structure and vertical data lines are prepared in advance through preliminary manufacturing steps, allowing chalcogenide material to be introduced intact in late-stage processing. This approach maintains chalcogenide material integrity while achieving seamless integration with the pre-formed structure
Solution Approach 2:
The vertical data lines serve as intermediaries that bridge the alternating stack and chalcogenide material plugs. By establishing this intermediate structure first, the chalcogenide material can be precisely positioned and integrated without degradation, combining ease of manufacture with high precision
3Reliability
If vertical data lines and chalcogenide material plugs are integrated, then electrical coupling is achieved, but manufacturing complexity increases
Solution Approach 1:
The integration process is divided into manageable segments: trench formation, vertical data line introduction, and chalcogenide material plug placement. Each segment addresses a specific aspect of electrical coupling, making the overall complex process more controllable and manufacturable
Solution Approach 2:
The alternating stack and vertical data lines are prepared in advance, creating a ready framework for chalcogenide material integration. This preliminary preparation reduces the complexity of the final integration step while ensuring reliable electrical coupling is achieved
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances manufacturing efficiency and performance of 3D vertical chalcogenide memory devices by ensuring reliable electrical coupling and maintaining chalcogenide material integrity, leading to improved memory operations.
Implementation Method 1
utilizing high-K materials for ohmic contacts and preserving chalcogenide material integrity through late-stage integration
Data Source
AI summary
Apparatus and methods are disclosed, including chalcogenide memory cells, semiconductor devices and systems. Example semiconductor devices and methods include a number of chalcogenide material plugs electrically isolated from one another. The number of chalcogenide material plugs are electrically coupled between conducting word line layers and a number of vertical data lines.