Vertical Memory Contact Plug Isolation in Staircase Gate Stacks

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In VNAND flash memory devices, the formation of contact plugs to connect gate electrodes is challenging due to varying heights of the gate electrode surfaces, which can lead to electrical shorts between the desired gate electrode and underlying electrodes.

Innovation Solution

A vertical memory device design featuring gate electrodes stacked in a staircase arrangement, with contact plugs extending through multiple gate electrodes and spacers to ensure electrical insulation from adjacent gate electrodes, and burying patterns made of insulating material for further isolation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If contact plugs are formed to connect gate electrodes with varying heights, then electrical connection is achieved, but electrical shorts occur between the desired gate electrode and underlying electrodes

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidelectrical shorts
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces spacers as intermediary insulating structures positioned between the contact plug and the sidewalls of gate electrodes. These spacers act as mediators that prevent direct electrical contact between the conductive contact plug and adjacent gate electrodes, thereby eliminating electrical shorts while maintaining the necessary electrical connections.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the problematic direct contact interface between the contact plug and gate electrode sidewalls by removing the conductive path through the application of insulating spacers. This separation takes out the harmful electrical connection while preserving the intended functional connections through the contact plug.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If spacers are added to prevent electrical shorts, then electrical insulation is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical insulationVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The spacers serve multiple functions simultaneously: they provide electrical insulation between the contact plug and gate electrodes, define the lateral boundaries of the contact plug region, and serve as structural support during subsequent processing steps. This multi-functionality reduces the need for additional separate structures, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If contact plugs extend through multiple gate electrodes, then electrical connection is established, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidcontact plug alignment
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The spacers are formed beforehand to define the precise lateral boundaries and depth limits for contact plug formation. This preliminary structuring establishes clear stop points and alignment references during the contact plug fabrication process, thereby reducing the actual manufacturing precision requirements during the critical contact plug deposition step.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12268003B2Vertical memory devices
Publication Date: 2025.04.01 SAMSUNG ELECTRONICS CO LTD
  • US12268003B2 patent drawing
  • US12268003B2 patent drawing
  • US12268003B2 patent drawing

AI summary

A vertical memory device including gate electrodes on a substrate, the gate electrodes being spaced apart in a first direction and stacked in a staircase arrangement; a channel extending through the gate electrodes in the first direction; a first contact plug extending through a pad of a first gate electrode to contact an upper surface of the first gate electrode, the first contact plug extending through a portion of a second gate electrode, and the second gate electrode being adjacent to the first gate electrode; a first spacer between the first contact plug and sidewalls of the first gate electrode and the second gate electrode facing the first contact plug, the first spacer electrically insulating the first contact plug from the second gate electrode; and a first burying pattern contacting bottom surfaces of the first contact plug and the first spacer, the first burying pattern including an insulating material.