Vertical Semiconductor Memory With Quadrangular Hole Pattern
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Solution Overview
Problem
Current semiconductor devices face challenges in miniaturization, low power consumption, and high performance while maintaining multi-functionality, particularly in storing data using variable resistance states effectively.
Innovation Solution
The design involves a semiconductor memory device with a stack of dielectric layers and electrodes, featuring a quadrangular hole pattern with variable resistance layers between the electrodes, allowing for increased integration and improved operating characteristics by using materials like transition metal oxides and perovskite-based materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If semiconductor devices are miniaturized to increase integration density, then device size is reduced, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent transitions from planar 2D memory structures to vertical 3D stacked structures. Multiple dielectric layers and electrode structures are stacked in the vertical direction, allowing increased storage density without increasing the planar footprint. This dimensional transition enables continued miniaturization while maintaining manufacturing feasibility through established vertical fabrication processes.
Solution Approach 2:
The patent implements nested structures where horizontal electrodes are positioned within grooves formed in dielectric layers, and vertical electrode structures extend through multiple stacked layers. The variable resistance layers are embedded within the stack structure, creating a nested arrangement that maximizes space utilization and integration density while maintaining structural integrity.
2Quantity of substance
If more memory cells are integrated in the same area, then storage capacity increases, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent creates a universal stacked memory structure where the same basic building block (dielectric layer with embedded electrodes and variable resistance layers) can be replicated multiple times in the vertical direction. This modular approach allows storage capacity to be increased by simply adding more stacked layers rather than complicating the lateral structure, maintaining fabrication simplicity while scaling capacity.
Solution Approach 2:
The patent divides the memory structure into discrete stacked segments, each comprising dielectric layers, horizontal electrodes, vertical electrodes, and variable resistance layers. Each segment can be independently fabricated and then stacked, allowing complex high-capacity structures to be built from simpler modular units, thereby managing device complexity through segmentation.
3Productivity
If variable resistance layers are disposed in grooves between electrodes, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms grooves in the dielectric layers before depositing the variable resistance layers and electrode structures. This preliminary groove formation creates pre-defined pathways that guide subsequent material deposition, ensuring precise positioning of variable resistance layers without requiring high-precision alignment during later fabrication steps. The grooves act as templates that simplify subsequent manufacturing operations.
Data Source
AI summary
An electronic device may include a semiconductor memory. The semiconductor memory may include a stack in which a plurality of dielectric layers and a plurality of first electrodes are alternately stacked over a substrate in a vertical direction relative to the substrate; a hole pattern passing through the stack in the vertical direction and having a polygonal shape when viewed in a plan view; a plurality of second electrodes disposed on respective sidewalls of the hole pattern; and a plurality of variable resistance layers interposed between the plurality of second electrodes and the plurality of horizontal electrodes.