Vertical Memory Device Structure with Quadrilateral Cell Sharing

The patent transitions from a planar memory cell layout to a three-dimensional vertical structure. Memory cells are stacked vertically above a single transistor, with conductive layers and memory structures extending in the vertical dimension. This allows multiple memory cells to share one transistor without increasing the footprint area, while the vertical stacking provides a clear hierarchical organization that manages complexity through spatial separation.

The vertical memory structure is divided into discrete, repeatable layers including conductive layers, memory structures, and interconnection lines. Each layer can be formed through separate fabrication steps using standard semiconductor processes such as atomic layer deposition (ALD) for conductive layers and spacer formation for memory structures. This segmentation allows complex three-dimensional structures to be built using simple, scalable two-dimensional processes repeated multiple times.

The conductive layers serve multiple functions simultaneously: they act as electrodes for memory cell operation, as interconnection lines for signal routing, and as structural elements for maintaining the vertical architecture. The same conductive material layers are used for both bit line and word line connections to different memory cells, eliminating the need for separate dedicated interconnection structures and reducing overall interconnection complexity.