Vertical Memory Resistive Layer Thickness Gradient
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in maintaining uniform operation electric field strength across vertically stacked memory cells, leading to potential malfunctions due to voltage drops as cells are disposed at varying distances from the voltage supplying end.
Innovation Solution
The semiconductor memory unit incorporates a resistive variable layer with varying thicknesses, positioned between vertical and horizontal electrodes, to ensure a uniform operation electric field strength across all memory cells, regardless of their distance from the voltage supplying end, using materials like perovskite-based oxides, transition metal oxides, or chalcogenide compounds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are vertically stacked to increase storage capacity, then storage density is improved, but voltage drops occur due to varying distances from the voltage supplying end, worsening operation reliability
Solution Approach 1:
The patent applies local quality by varying the thickness of the resistive variable layer at different vertical positions. Memory cells closer to the voltage supplying end have thicker resistive variable layers, while those farther away have thinner layers. This compensates for voltage drops by providing higher resistance where voltage is stronger and lower resistance where voltage is weaker, maintaining uniform operation across all stacked cells.
2Quantity of substance
If memory cells are disposed at varying distances from the voltage supplying end to enable vertical stacking, then storage density is improved, but electric field strength becomes non-uniform, worsening operation uniformity
Solution Approach 1:
The patent implements local quality by making the resistive variable layer thickness position-dependent. Cells at different vertical positions have differently thickened resistive variable layers, creating local variations in electrical characteristics that compensate for the non-uniform electric field distribution caused by vertical stacking geometry.
3Ease of manufacture
If uniform resistive variable layer thickness is used across all memory cells, then manufacturing simplicity is maintained, but voltage drops cause non-uniform operation, worsening device performance
Solution Approach 1:
The patent resolves this contradiction by introducing local quality variations in the resistive variable layer thickness. While this increases manufacturing complexity compared to uniform thickness, it enables uniform device performance across all stacked memory cells by compensating for voltage drops through position-specific thickness adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of the semiconductor memory unit by maintaining consistent operation electric field strength across all memory cells, improving the overall performance and reducing the risk of malfunctions caused by voltage drops.
Implementation Method 1
maintaining a more uniform operation electric field strength, even though the memory cells are disposed at a plurality of distances from an operation voltage supplying end
Data Source
AI summary
An electronic device includes a semiconductor memory unit that includes a vertical electrode formed over a substrate and receiving a voltage through one end of the vertical electrode, a resistance variable layer formed along a side of the vertical electrode to be thinner going from one end to the other end, and a plurality of horizontal electrodes formed adjacent to the vertical electrode with the resistance variable layer disposed between the horizontal electrodes and the vertical electrode, and stacked over the substrate with a space from each other.