Vertical Memory Arrays with Rounded-Nose Gates for Charge-Trapping Control
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Solution Overview
Problem
Existing memory cell designs and array architectures, particularly in NAND memory arrays, face challenges in achieving improved performance in terms of control over charge-trapping, reduced disturbance between vertically-adjacent cells, and faster programming speeds.
Innovation Solution
The development of memory arrays with vertically-stacked conductive segments featuring rounded-nose transistor gates and specific material configurations, including charge-blocking and charge-storage materials, along with dielectric barriers and tunneling structures, to enhance control over charge storage and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory cell designs are used, then manufacturing is simpler, but control over charge-trapping is insufficient and disturbance between vertically-adjacent cells increases
Solution Approach 1:
The memory cell structure is segmented into distinct functional regions including charge-blocking regions, charge-storage regions, and dielectric barrier regions. This segmentation allows independent optimization of each region's properties to improve charge-trapping control while maintaining manageable manufacturing complexity through modular design.
Solution Approach 2:
Different materials and structures are applied to different locations within the memory cell. Specifically, charge-blocking material is placed between the channel and control gate, dielectric barriers are positioned at specific interfaces, and charge-storage material is located in predetermined regions. This local differentiation enables precise control over charge-trapping behavior without requiring complete structural redesign.
2Productivity
If conventional memory cell designs are used, then device structure is simpler, but programming speed is slower
Solution Approach 1:
The patent extracts and separates the charge-storage function from the conventional floating gate structure by introducing dedicated charge-storage material in specific regions. This extraction allows for optimized charge injection and storage mechanisms that enable faster programming speeds while the separated structure maintains manufacturing feasibility.
Solution Approach 2:
The patent modifies key structural parameters including the introduction of dielectric barriers with specific thicknesses, charge-blocking regions with controlled dimensions, and charge-storage material with optimized properties. These parameter changes enhance programming speed by improving charge injection efficiency and reducing storage time while keeping the overall device complexity within acceptable limits.
3Quantity of substance
If vertically-stacked memory cells are used, then storage density increases, but disturbance between adjacent cells increases
Solution Approach 1:
Dielectric barrier material is introduced as an intermediary layer between vertically-adjacent memory cells. This intermediary structure electrically isolates adjacent cells, preventing charge leakage and disturbance between cells while maintaining the high storage density benefits of vertically-stacked architecture.
Solution Approach 2:
The patent extracts potential sources of interference by removing direct electrical coupling between adjacent vertically-stacked cells through the use of charge-blocking regions and dielectric barriers. This extraction of harmful electrical interactions allows high-density vertical stacking without suffering from cell-to-cell disturbance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables improved control over charge-trapping, reduces disturbance between adjacent memory cells, and facilitates faster programming speeds and improved retention, enhancing overall memory array performance.
Implementation Method 1
charge-blocking material between the channel material and gate
Implementation Method 2
charge-storage material adjacent the charge-blocking material
Implementation Method 3
dielectric barrier material between the gate and rounded noses of adjacent gates
Implementation Method 4
gates have rounded noses which encompass the first ends. The rounded noses are spaced from the channel material
Data Source
AI summary
Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.