Vertical Memory Device Fabrication via Alternating Sacrificial Layers
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Solution Overview
Problem
As the design rule decreases and integration increases in memory devices, there is a need for structures that ensure both structural stability and reliability of storage operations, particularly in three-dimensional storage cell structures like cross-point structures, which face challenges in maintaining effective storage and access to information.
Innovation Solution
A method of fabricating a vertical memory device involving a stack structure with alternating sacrificial layers, trench formation, channel layer coverage, selective removal of sacrificial layers to form recesses, and subsequent deposition of conductive, interfacial insulation, ferroelectric, and gate electrode layers to create functional memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional high aspect ratio capacitors are used in memory cells, then storage capacity can be achieved, but structural stability and reliability deteriorate
Solution Approach 1:
The patent transitions from planar capacitor structures to vertical three-dimensional cross-point structures. Memory cells are formed at the intersections of vertical word lines and bit lines, with storage nodes positioned at these cross-points. This dimensional change enables higher storage capacity while maintaining structural stability through the distributed three-dimensional architecture rather than relying on single high aspect ratio capacitors.
Solution Approach 2:
The memory array is segmented into multiple word lines and bit lines that intersect to form discrete memory cells. Each memory cell is independently formed at a cross-point with its own storage node, allowing distributed storage capacity without requiring single high aspect ratio structures. This segmentation provides both increased capacity and improved reliability through redundancy and distributed architecture.
2Productivity
If design rule decreases and integration increases, then storage density improves, but maintaining structural stability and reliable storage operation becomes difficult
Solution Approach 1:
The patent employs vertical three-dimensional cross-point structures where word lines and bit lines extend in vertical and lateral dimensions respectively. This multi-dimensional arrangement enables high storage density within limited footprint while maintaining reliable storage operation through the geometric stability of intersecting lines and nodes, avoiding the high aspect ratio problems of conventional vertical capacitors.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions: conductive materials for word and bit lines, insulating materials for spacing and isolation, and specific materials for storage nodes. This local optimization of material properties ensures structural stability and reliable operation at each cross-point while enabling overall high integration density.
Data Source
AI summary
In a method, a stack structure including a plurality of first interlayer sacrificial layers and a plurality of second interlayer sacrificial layers that are alternately stacked is formed over a substrate. A trench penetrating the stack structure is formed. A channel layer covering a sidewall surface of the trench is formed. The plurality of first interlayer sacrificial layers are selectively removed to form a plurality of first recesses. The plurality of first recesses are filled with a conductive material to form a plurality of channel contact electrode layers. The plurality of second interlayer sacrificial layers are selectively removed to form a plurality of second recesses. A plurality of interfacial insulation layers, a plurality of ferroelectric layers and a plurality of gate electrode layers are formed in the plurality of second recesses.