Vertical Memory Structures with Segmented Stack Regions

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Solution Overview

Problem

Current semiconductor devices face challenges in increasing data storage capacity effectively, particularly in designing efficient three-dimensional memory structures that maintain alignment and contact integrity between vertical memory structures and separation structures.

Innovation Solution

The semiconductor device incorporates a stack structure with alternating interlayer insulating layers and gate electrodes, featuring vertical memory structures and separation structures that are strategically spaced and shaped to ensure precise alignment and contact, with bitline contact plugs electrically connected to the vertical memory structures, enhancing data storage capacity and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If vertical memory structures are densely arranged to increase storage capacity, then data storage capacity is improved, but alignment precision between vertical memory structures and separation structures deteriorates

Engineering Contradiction:
Improvedata storage capacityVSAvoidalignment precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The memory device is divided into multiple stack regions separated by separation structures. Each stack region contains vertically stacked memory cells, and the separation structures physically divide these regions while maintaining precise alignment through the segmented architecture. This segmentation allows dense vertical arrangement within each region while preserving manufacturing precision through structured separation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from two-dimensional planar memory structures to three-dimensional vertically stacked structures. Memory cells are arranged in multiple layers along the vertical dimension, with separation structures extending through multiple stack regions. This dimensional change enables increased storage capacity without compromising alignment precision, as the separated structures provide reference planes for maintaining vertical alignment across layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If separation structures are extended deeper to improve alignment, then alignment precision is improved, but device complexity increases

Engineering Contradiction:
Improvealignment precisionVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The separation structures serve multiple functions simultaneously: they physically separate adjacent stack regions, provide alignment references for vertical structures, and act as isolation barriers. By making the separation structures multi-functional, the design achieves improved alignment precision without proportionally increasing complexity, as the same structural elements fulfill multiple roles in the device architecture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230057630A1Semiconductor device and data storage system including the same
Publication Date: 2023.02.23 SAMSUNG ELECTRONICS CO LTD
  • US20230057630A1 patent drawing
  • US20230057630A1 patent drawing
  • US20230057630A1 patent drawing

AI summary

A device includes: a stack structure including first and second stack regions; first and second separation structures penetrating the stack structure; and vertical structures penetrating the stack structure, including first and second vertical memory structures spaced from the first separation structure by different lengths. The first and second vertical memory structures each include a lower portion, penetrating the first stack region, and an upper portion penetrating the second stack region. A first distance between a center of an upper region of the upper portion of the first vertical memory structure and a center of an upper region of the upper portion of the second vertical memory structure is different from a second distance between a center of an upper region of the lower portion of the first vertical memory structure and a center of an upper region of the lower portion of the second vertical memory structure.