Vertical Memory Devices With Segmented Charge Trapping
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Solution Overview
Problem
There is a limitation in scaling down the size of vertical memory devices beyond a certain level, which affects their integration and electrical characteristics.
Innovation Solution
The design includes gate electrodes and a channel with a tunnel insulation pattern, charge trapping pattern structures, and blocking pattern structures formed on the outer sidewall of the channel, where the charge trapping patterns are spaced apart vertically and the tunnel insulation pattern protrudes towards the gate electrodes, enhancing electron injection and reducing interference between gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of each vertically-stacked layer is reduced to improve integration, then the degree of integration is improved, but scaling down beyond a certain level becomes limited
Solution Approach 1:
The patent transitions from planar 2D memory architecture to vertical 3D architecture by stacking multiple layers in the vertical direction. This dimensional change allows continued scaling and integration improvement without being constrained by planar manufacturing precision limits, as the vertical stacking enables higher density through the third dimension.
Solution Approach 2:
The patent implements nested structures where charge trapping patterns are positioned within recesses of the channel, and tunnel insulation patterns are formed within recesses of the charge trapping patterns. This nested arrangement maximizes space utilization within each vertical layer, enabling higher integration without increasing the footprint area.
2Ease of manufacture
If conventional vertical memory structures are used, then manufacturing is simpler, but electrical characteristics and integration degree are limited
Solution Approach 1:
The patent segments the channel structure by forming recesses at different depths and positions along the channel. These segmented recesses accommodate different functional patterns (charge trapping, tunnel insulation) at specific locations, allowing each segment to perform its designated function optimally while maintaining overall manufacturability through standardized fabrication processes.
Solution Approach 2:
The patent applies local quality by positioning charge trapping patterns and tunnel insulation patterns at specific localized regions rather than uniformly throughout the channel. The charge trapping patterns are placed in recesses at predetermined depths, and tunnel insulation patterns are formed in recesses of the charge trapping patterns, creating locally optimized structures that enhance electrical characteristics without complicating the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the integration degree and electrical characteristics of vertical memory devices by allowing efficient electron injection and minimizing coupling between gate electrodes.
Implementation Method 1
A tunnel insulation pattern is disposed on a portion of an outer sidewall of the channel... Charge trapping pattern structures are disposed between the tunnel insulation pattern and each of the gate electrodes
Data Source
AI summary
A vertical memory device includes gate electrodes disposed on a substrate and spaced apart from each other in a vertical direction. A channel extends in the vertical direction and is positioned adjacent to the gate electrodes. A tunnel insulation pattern is disposed on a portion of an outer sidewall of the channel that is adjacent to each of the gate electrodes. Charge trapping pattern structures are disposed between the tunnel insulation pattern and each of the gate electrodes. Each of the charge trapping pattern structures includes upper and lower charge trapping patterns spaced apart from each other in the vertical direction. Blocking pattern structures are between the charge trapping patterns and each of the gate electrodes. A first portion of the channel that is adjacent to the tunnel insulation pattern has a thickness in a horizontal direction that is smaller than a thickness of other portions of the channel.