3D Memory Stack With Vertical Select Transistors for Logic Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in integrating high-density embedded memory arrays with logic circuits, particularly in efficiently forming memory cells that are compatible with nano-scale logic circuits and require advanced manufacturing processes.
Innovation Solution
The semiconductor device incorporates a front-end-of-line (FEOL) and back-end-of-line (BEOL) portions, with memory cells featuring resistive random access memory (RRAM), phase change random access memory (PCRAM), and magnetoresistive random access memory (MRAM) cells, utilizing advanced processes like CVD, ALD, and etching techniques to form memory stacks and select transistors, enabling efficient integration and reduced footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar memory structures are used, then manufacturing processes are simpler, but memory density and integration with logic circuits are limited
Solution Approach 1:
The patent transitions from planar (2D) memory structures to three-dimensional (3D) vertically stacked memory cells. Multiple memory stacks are formed vertically over active regions, with bit lines extending in first directions and word lines in second directions perpendicular to the bit lines. This vertical stacking approach dramatically increases memory density by utilizing the third dimension (height) rather than only horizontal plane expansion.
2Adaptability or versatility
If memory cells are formed with advanced nano-scale processes, then integration with logic circuits improves, but manufacturing complexity increases
Solution Approach 1:
The memory device is segmented into distinct functional components: multiple memory stacks vertically arranged over active regions, bit lines extending in first directions, and word lines extending in second directions. Each stack contains sequentially deposited layers including bottom electrodes, memory material layers, and top electrodes. This segmentation allows independent optimization and fabrication of each component using compatible nano-scale processes while maintaining overall integration.
Solution Approach 2:
The patent employs universal fabrication processes including chemical vapor deposition (CVD), atomic layer deposition (ALD), and etching techniques that can be applied across both logic circuit fabrication and memory cell formation. The sequentially deposited layers in each memory stack can be formed using the same deposition and patterning tools used for logic circuits, enabling seamless integration without requiring separate manufacturing lines.
3Quantity of substance
If vertically stacked memory structures are implemented, then memory density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs sequential deposition of multiple layers (bottom electrodes, memory material layers, top electrodes) in a predetermined order before final patterning. Each layer is deposited with controlled thickness and composition, and preliminary patterning steps are performed to define regions before subsequent layer formation. This preliminary action approach allows precise control of vertical stack dimensions and alignment, reducing the precision burden on final etching steps.
Solution Approach 2:
The patent utilizes controlled changes in deposition parameters (temperature, pressure, gas flow rates) and etching parameters (power, gas composition, etch rate) to precisely control the dimensions, composition, and properties of each layer in the vertical stacks. By adjusting these parameters during sequential deposition and etching processes, the manufacturing precision is maintained even as memory density increases through vertical stacking.
Data Source
AI summary
A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.