Vertical Memory Block Slot Spacing Optimization
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Solution Overview
Problem
Conventional methods for forming through-array vias in vertical memory arrays require additional complex processing steps and materials, increasing costs and complexity.
Innovation Solution
The formation of vertical memory blocks with conductive vias is optimized by varying the distance between slots in different regions, allowing for the integration of conductive vias within existing dielectric stacks without the need for additional material removal, using alternating dielectric materials to electrically isolate the vias from conductive word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form through-array vias in vertical memory arrays, then electrical connectivity and memory density are achieved, but the number of processing steps and manufacturing complexity increase
Solution Approach 1:
The patent combines the formation of through-array vias with the existing dielectric stack structure. The vias are formed by selectively removing portions of the alternating dielectric layers that were already deposited for word line plate formation, rather than adding separate via formation steps. This merging of operations reduces overall manufacturing complexity while maintaining electrical connectivity.
Solution Approach 2:
The alternating dielectric stack serves multiple functions: it provides electrical isolation between conductive word line plates and simultaneously provides the material structure through which through-array vias are formed. This multi-functionality eliminates the need for additional dedicated via formation layers or structures, reducing processing steps while achieving both isolation and connectivity.
2Reliability
If additional material removal is performed to form through-array vias, then electrical isolation is achieved, but manufacturing cost and process complexity increase
Solution Approach 1:
The alternating dielectric layers are deposited in advance during the normal word line plate formation process, before via formation is needed. These pre-deposited dielectric layers already provide the necessary electrical isolation structure. When through-array vias are subsequently formed by selective removal of these pre-existing dielectric portions, the isolation function is already built-in, eliminating the need for additional isolation materials or processes.
Solution Approach 2:
The dielectric stack structure serves itself by providing both the isolation function and the template for via formation. The same alternating dielectric layers that provide electrical isolation between conductive plates also define the regions where through-array vias will be formed through selective removal. This self-service approach reduces manufacturing cost by eliminating the need for separate isolation structures.
3Productivity
If slots are placed closer together to increase memory density, then more memory cells fit in the array, but electrical isolation between conductive elements becomes more difficult
Solution Approach 1:
The patent changes the parameter of dielectric layer thickness in the alternating stack. By controlling the thickness of the dielectric layers to be sufficient for electrical isolation even when slots are closely spaced, the design achieves both high memory density and reliable electrical isolation. The dielectric thickness parameter is optimized to provide adequate isolation at reduced slot pitch.
Solution Approach 2:
The patent uses alternating layers of different dielectric materials with different properties. Some layers provide superior electrical isolation characteristics while others provide mechanical support or etch selectivity. This composite dielectric stack structure achieves effective electrical isolation between closely spaced slots by combining the advantages of multiple dielectric materials.
Data Source
AI summary
Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a dielectric stack of alternating dielectric materials and at least one conductive via extending through the dielectric stack. Semiconductor devices including a vertical memory block include at least one vertical memory block, which includes slots extending between adjacent memory cells of a three-dimensional array. The slots are separated by a first distance in a first portion of the block, and by a second, greater distance in a second portion of the block. Methods of forming vertical memory blocks include forming slots separated by a first distance in a memory array region and by a second, greater distance in a via region. At least one conductive via is formed through a stack of alternating first and second dielectric materials in the via region.