Vertical Memory Common Source Layout for Lower WL-ACS Leakage
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Solution Overview
Problem
Existing 3D NAND flash memory technologies face issues with word line to ACS leakage, large word line to ACS capacitance, and process stress due to ACS contacts formed in gate line cut structures, which hinder efficient current distribution and area utilization in vertical memory devices.
Innovation Solution
The implementation of a high conductive layer as a common source layer extending into a staircase region, with ACS contacts formed in the staircase region, allowing for efficient current distribution and flexible contact placement, reducing the need for additional masks and process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ACS contacts are formed in gate line cut structures, then current distribution is achieved, but word line to ACS leakage occurs and large capacitance is generated
Solution Approach 1:
The patent extracts the ACS contact formation from the gate line cut structure by introducing a separate staircase region. This spatial separation eliminates the harmful interaction between word lines and ACS contacts, removing the source of leakage and capacitance while preserving current distribution functionality.
Solution Approach 2:
The staircase region acts as an intermediary structure that facilitates ACS contact formation without direct interaction with gate line cuts. This mediator structure enables current distribution while preventing the harmful electrical coupling between word lines and ACS contacts.
2Reliability
If ACS contacts are formed in gate line cut structures, then current distribution is achieved, but process stress occurs
Solution Approach 1:
The patent removes ACS contact formation from the gate line cut process sequence by establishing a dedicated staircase region. This extraction eliminates the process stress caused by forming contacts in gate line cuts while maintaining current distribution capability through the separated staircase structure.
3Adaptability or versatility
If common source layer is extended into staircase region, then contact placement flexibility is improved, but device structure complexity increases
Solution Approach 1:
The common source layer is designed to serve multiple functions: it acts as the source for memory cells in the array region and extends into the staircase region to provide contact formation capability. This multi-functional design enables flexible contact placement without requiring additional specialized structures, thereby avoiding increased complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes word line to ACS leakage, eliminates large capacitance, and reduces process stress, enabling a smaller core region for the same memory capacity while improving current distribution and area efficiency in vertical memory devices.
Implementation Method 1
The common source layer includes a metal silicon compound layer and a silicon layer. The metal silicon compound layer includes at least one of titanium (Ti), cobalt (Co), nickel (Ni), and platinum (Pt).
Data Source
AI summary
Aspects of the disclosure provide a semiconductor device and method. An example method include forming a stack of layers on a substrate, the stack of layers including a source sacrificial layer, a conductive layer, gate sacrificial layers and insulating layers; forming a staircase into the stack of layers in a staircase region that is adjacent to an array region; forming channel structures in the array region, a channel structure including a channel layer surrounded by one or more insulating layers and extending into the stack of layers; replacing the source sacrificial layer with a source layer in conductive connection with the channel layer, the source layer and the conductive layer forming a common source layer; replacing the gate sacrificial layers with gate layers; and forming a first contact structure in the staircase region, the first contact structure forming a conductive connection with the common source layer.