Vertical Memory Stack with Shared Source Line for Warpage Control
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Solution Overview
Problem
Existing semiconductor memory devices with nonvolatile memory structures face challenges in achieving a stable structure and improved characteristics, particularly in terms of write and read speeds, which are slower compared to volatile memory devices.
Innovation Solution
A semiconductor memory device is designed with a vertical channel structure, featuring a first stack structure with first slits extending in a horizontal direction, and a second stack structure with second slits extending in a perpendicular horizontal direction. This configuration allows for direct bonding of source line layers between the memory chip structures, improving warpage phenomena and enabling shared source line layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chip structures are bonded vertically to increase storage capacity, then the storage density is improved, but warpage phenomena occur at the interface between chip structures
Solution Approach 1:
The patent introduces slits that divide the stack structures into multiple segments. These slits allow the structure to accommodate thermal expansion and contraction differences between bonded memory chip structures, reducing warpage at interfaces while maintaining high storage capacity through vertical stacking.
Solution Approach 2:
The patent applies different structural characteristics to different regions: slits are introduced in specific locations within the stack structure where warpage is most likely to occur, while other regions maintain their original structure for optimal electrical performance. This localized modification addresses warpage issues without compromising overall device functionality.
2Device complexity
If source line layers are shared between bonded memory chip structures to reduce complexity, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges source line layers from multiple memory chip structures into a shared structure. By bonding memory chip structures vertically and sharing common source line layers, the overall device complexity is reduced while maintaining electrical functionality across all stacked components.
Solution Approach 2:
The patent performs preliminary alignment and bonding of memory chip structures before finalizing the source line layer configuration. This preliminary action ensures that subsequent source line sharing can be implemented with appropriate precision, reducing the burden on final manufacturing steps.
3Speed
If vertical channel structures are used to improve write and read speeds, then access speed is improved, but structural stability becomes more challenging
Solution Approach 1:
The patent segments the vertical stack structure by introducing slits that divide the continuous vertical channels into manageable sections. This segmentation maintains the vertical channel architecture necessary for fast access speeds while providing structural break points that enhance overall stability and reduce stress accumulation in the vertical structure.
Data Source
AI summary
The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first stack structure, a plurality of first slits passing through the first stack structure in a vertical direction and extending in a first horizontal direction orthogonal to the vertical direction, a first source line layer contacting an a top portion of the first stack structure, a second source line layer directly contacting the first source line layer, a second stack structure contacting the second source line layer and overlapping with the first stack structure in the vertical direction, and a plurality of second slits passing through the second stack structure in the vertical direction and extending in a second horizontal direction orthogonal to the vertical direction.