Vertical Memory Cell Layout With Split Page Buffers
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Solution Overview
Problem
Existing memory devices face challenges in integrating operations circuits and wiring structures due to the complexity of non-volatile memory devices, particularly in three-dimensional memory cell arrays, which restricts the degree of integration and efficient use of space.
Innovation Solution
A memory device with a vertical structure is designed, where lower semiconductor layers include portions of page buffers and row decoders, allowing for a Cell-On-Peri (COP) structure that overlaps with upper memory cell arrays, enabling independent control and reducing the planar area occupied by peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are stacked three-dimensionally to improve integration, then the degree of integration is improved, but operation circuits and wiring structures become complicated
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacking of memory cell arrays. Multiple memory cell arrays are stacked vertically in the third direction, allowing higher integration density while managing complexity through vertical separation of circuits and arrays.
Solution Approach 2:
The patent divides the memory device into multiple stacked layers, with each layer containing specific memory cell arrays and peripheral circuits. This segmentation allows independent design and optimization of each layer, reducing overall system complexity while improving integration.
2Device complexity
If peripheral circuits are placed in separate planar regions, then circuit operations are simplified, but the overall device area increases
Solution Approach 1:
The patent implements a Cell-On-Peri structure where memory cell arrays are positioned to overlap with peripheral circuits in the vertical direction. This nesting allows peripheral circuits to be placed in regions that would otherwise be unused, reducing the overall planar area while maintaining circuit functionality.
Solution Approach 2:
The patent utilizes the vertical dimension to resolve area conflicts. Memory cell arrays and peripheral circuits that would conflict in planar layout are separated vertically, allowing both to coexist in the same footprint area without increasing the overall device area.
3Quantity of substance
If more memory cell arrays are integrated, then storage capacity increases, but the number of page buffers required increases device complexity
Solution Approach 1:
The patent designs page buffers to serve multiple memory cell arrays. A single page buffer can be shared among multiple memory cell arrays through vertical stacking and appropriate wiring, reducing the total number of page buffers needed while maintaining storage capacity.
Solution Approach 2:
The patent combines multiple memory cell arrays that can share common peripheral circuits including page buffers. By merging the support infrastructure for multiple arrays, the device achieves high storage capacity without proportionally increasing the number of page buffers.
Data Source
AI summary
A memory device includes a first lower semiconductor layer and a second lower semiconductor layer. The first lower semiconductor layer is disposed below a first upper semiconductor layer including a first memory cell array. The first lower semiconductor layer includes a first page buffer electrically connected to the first memory cell array. The second lower semiconductor layer is disposed below a second upper semiconductor layer includes a second memory cell array and disposed adjacent to the first upper semiconductor layer in a first direction. The second lower semiconductor layer includes a first portion of a second page buffer electrically connected to the second memory cell array and being disposed adjacent to the first lower semiconductor layer in the first direction. The first lower semiconductor layer further includes a second portion of the second page buffer different from the first portion.