Vertical Memory Cell Stack Layout for High-Density DRAM
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Solution Overview
Problem
The challenge in semiconductor memory devices is achieving high integration while maintaining effective electrical connections and preventing disturbance between memory cells, which is difficult with traditional planar channel transistors.
Innovation Solution
The semiconductor memory device incorporates vertical channel transistors with specific configurations, including multiple cell stacks and connection contacts, to enable high integration and efficient electrical connections between conductive lines and capacitor structures, ensuring that channel layers do not overlap vertically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar channel transistors are used, then manufacturing is simpler, but integration density is low
Solution Approach 1:
The patent transitions from planar (2D) channel transistors to vertical (3D) channel transistors, utilizing the vertical dimension to increase integration density. The channel layer extends vertically from the substrate through multiple interlayer insulating layers, enabling higher device density without complicating the fundamental transistor operation.
2Quantity of substance
If vertical channel transistors are used, then integration density increases, but electrical connection complexity increases
Solution Approach 1:
The patent divides the connection structure into multiple discrete components: first connection contacts connecting conductive lines to first channel layers, second connection contacts connecting first channel layers to capacitor structures, and third connection contacts connecting second channel layers to capacitor structures. This segmentation simplifies the overall connection architecture by creating modular, manageable connection paths.
Solution Approach 2:
The patent introduces intermediate connection elements (first and second connection contacts) that mediate between the vertical channel structures and horizontal conductive lines. These intermediaries facilitate electrical connection without requiring direct contact between vertically stacked components and horizontal wiring, simplifying the connection process.
3Quantity of substance
If channel layers are positioned closely for high density, then disturbance between adjacent cells increases
Solution Approach 1:
The patent positions first and second channel layers at different vertical levels within the stack, creating local spatial separation. The first channel layer is located between the substrate and first interlayer insulating layer, while the second channel layer is positioned higher, between the first and second interlayer insulating layers. This local vertical separation reduces capacitive coupling and interference between adjacent memory cells while maintaining high density.
Data Source
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AI summary
A semiconductor memory device including a substrate, a plurality of conductive lines extending in a first horizontal direction on the substrate and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, a first cell stack on each of the plurality of conductive lines and including a plurality of first vertical transistor structures and a plurality of first connection contacts, a second cell stack on the first cell stack and including a plurality of second vertical transistor structures and a plurality of second connection contacts, and a plurality of capacitor structures on the second cell stack and connected to the plurality of first vertical transistor structures and the plurality of second vertical transistor structures, wherein each of the plurality of first connection contacts is adjacent to one of the plurality of first vertical transistor structures and under one of the plurality of second vertical transistor structures, and electrically connects one of the plurality of conductive lines to one of the plurality of second vertical transistor structures, and wherein each of the plurality of second connection contacts is adjacent to one of the plurality of second vertical transistor structures and on one of the plurality of first vertical transistor structures, and electrically connects one of the plurality of first vertical transistor structures to one of the plurality of capacitor structures.