Vertical Memory Stack Layout With Widened Bit Line Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing two-dimensional nonvolatile memory devices have reached integration limits, necessitating the development of three-dimensional structures to enhance memory cell density and operational reliability.
Innovation Solution
A semiconductor memory device is designed with stacked conductive layers and vertical structures, including memory layers and channel patterns, isolated by insulating layers, to improve integration and connectivity between bit lines and memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional nonvolatile memory devices are used, then manufacturing simplicity is maintained, but the degree of integration reaches a limit
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional structure by stacking multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) vertically over the substrate. This dimensional change enables significantly higher integration density while maintaining manufacturability through standard semiconductor fabrication processes.
Solution Approach 2:
The memory device is segmented into multiple functional layers including stack structures with alternating insulating layers and gate electrodes, vertical structures with memory layers and channel patterns, and bit line contact structures. This segmentation allows each layer to perform specific functions while collectively achieving high integration.
2Quantity of substance
If bit line contact structure has conventional shape, then manufacturing is simple, but connectivity and integration efficiency are limited
Solution Approach 1:
The bit line contact structure is designed with an asymmetric shape that is widened toward the bit line compared to its base. This asymmetric geometry improves connectivity efficiency by providing better electrical contact area with the bit line while the widening portion is configured to prevent short circuits, thus enhancing integration efficiency without requiring excessive manufacturing precision.
Data Source
AI summary
A semiconductor memory device includes: a first stack structure and a second stack structure on a semiconductor substrate; a first vertical structure having a side all in contact with the first stack structure, the first vertical structure including a first memory layer and a first channel pattern; a second vertical structure having a sidewall in contact with the second stack structure, the second vertical structure including a second memory layer and a second channel pattern; a first bit line contact structure on the first vertical structure; and a first bit line overlapping with the first bit line contact structure. Each of the first stack structure and the second stack structure includes conductive layers stacked on the semiconductor substrate to be spaced apart from each other. The first bit line contact structure has a shape which is widened toward the first bit line.