Vertical Memory Cell Stack Wiring With Step-Shaped Contact Structure

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Solution Overview

Problem

The formation of wires becomes increasingly difficult as the stacked height of memory cells in bonding-type vertical semiconductor devices increases, making it challenging to maintain efficient wire connections.

Innovation Solution

The design incorporates pattern structures with a step-shaped edge region and embedded insulating patterns within trenches, along with channel structures and contact plugs that extend to upper insulating layers, ensuring consistent electrical connections and reducing wire complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the stacked height of memory cells is increased, then the storage capacity is improved, but the vertical height of wires increases making wire formation more difficult

Engineering Contradiction:
Improvestorage capacityVSAvoidwire formation
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from conventional planar wire formation to vertical wire formation through stacked pattern structures. By stacking insulating patterns and gate electrodes vertically, the device creates multiple levels for wire routing, allowing wires to extend vertically through contact plugs that penetrate through the stacked structures, thus solving the wire formation difficulty while maintaining increased storage capacity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the wire formation process into segmented sections corresponding to different stacked levels. Each pattern structure level contains its own set of contact plugs and wires, allowing independent formation and optimization of wire connections at each level, which simplifies the overall manufacturing process despite the increased vertical height

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12604724B2Vertical semiconductor device
Publication Date: 2026.04.14 SAMSUNG ELECTRONICS CO LTD
  • US12604724B2 patent drawing
  • US12604724B2 patent drawing
  • US12604724B2 patent drawing

AI summary

A vertical semiconductor device includes lower circuit patterns disposed on a first substrate. A bonding layer is disposed on the lower circuit patterns. A wire is disposed on the bonding layer. A cell stack structure is disposed on the wire. A base pattern is disposed on the cell stack structure. An upper insulating layer is disposed on the base pattern. A cell contact plug passes through the cell stack structure and extends to the upper insulating layer. A through-plug is disposed inside a through-hole formed through an outer side of the base pattern to extend to the upper insulating layer. Each of the cell contact plug and the through-plug includes a barrier metal pattern and a metal pattern, and the barrier metal pattern is disposed along sidewalls and bottom surfaces of the cell contact hole and the through-hole.