Vertical Memory Device Stacked Gate Architecture
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high capacity data processing while maintaining compact size, as they rely on planar transistor structures that limit integration and electrical performance.
Innovation Solution
A vertical memory device is designed with a stacked structure featuring gate electrode layers, channel layers extending perpendicular to the substrate, and a common source layer, along with separation patterns and conductive layers to enhance integration and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If planar transistor structure is used, then device fabrication is simple, but integration degree and electrical characteristics are limited
Solution Approach 1:
The patent transitions from a planar two-dimensional transistor structure to a vertical three-dimensional structure. The channel extends in the vertical direction perpendicular to the substrate, with gate electrodes wrapping around the channel from multiple directions. This dimensional change enables higher integration density while maintaining controllable fabrication processes through sequential layer deposition and patterning.
Solution Approach 2:
The gate electrodes are arranged in a nested configuration where multiple gate electrodes wrap around the channel in sequence. The first gate electrode is positioned at a first height, the second gate electrode at a second height, creating a nested vertical arrangement that maximizes space utilization and integration density within the vertical architecture.
Data Source
AI summary
A vertical memory device includes a stacked structure including a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers extending in a direction perpendicular to an upper surface of the substrate on a first side surface of the stacked structure and spaced apart from each other in a direction parallel to the upper surface of the substrate, and a common source layer disposed between the stacked structure and the substrate and contacting the channel layers.