Vertical Semiconductor Memory Device Structures with Stepped and Planar Profiles

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Solution Overview

Problem

Conventional two-dimensional semiconductor devices face limitations in integration density due to the need for expensive equipment to form fine patterns, prompting the development of three-dimensional semiconductor memory devices to overcome these limitations.

Innovation Solution

The development of vertical semiconductor memory device structures with vertical channel and dummy structures, featuring stepped and planar side walls, and a stack structure with alternating electrode and insulating layers, which allows for improved integration density and manufacturing efficiency through specific patterning and etching processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional two-dimensional semiconductor devices use fine pattern formation techniques to increase integration density, then integration density is improved, but manufacturing cost increases due to expensive apparatuses

Engineering Contradiction:
Improveintegration densityVSAvoidmanufacturing cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from two-dimensional planar structures to three-dimensional vertical structures by forming stack structures with alternating electrode and insulating layers that extend vertically. This dimensional change allows integration density to increase without requiring progressively finer lateral patterning, thereby avoiding the need for increasingly expensive lithography equipment while achieving higher cell densities through vertical stacking.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If vertical channel structures with stepped profiles are formed in the cell array region, then integration density is improved, but device complexity increases

Engineering Contradiction:
Improveintegration densityVSAvoidstructure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The vertical channel structure is segmented into two distinct regions: a first region in the cell array with a stepped profile that interfaces with the stack structure, and a second region in the connection region with a substantially cylindrical profile. This segmentation allows each region to be optimized independently—the stepped profile maximizes integration density in the cell array by efficiently packing vertical channels around the stack, while the cylindrical profile simplifies manufacturing and electrical connection in the connection region, thereby reducing overall device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different geometric profiles are applied to different spatial locations of the vertical channel structure based on local functional requirements. The stepped profile is localized to the cell array region where maximum packing density is needed, while the cylindrical profile is localized to the connection region where manufacturing ease and electrical performance are prioritized. This local differentiation resolves the contradiction by optimizing each region for its specific function rather than applying a uniform complex structure throughout.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If vertical dummy structures with planar profiles are formed in the connection region, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvepatterning precisionVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Vertical dummy structures are introduced as intermediary elements in the connection region between the vertical channel structures and the external connection interfaces. These dummy structures with substantially planar side walls serve as buffer or transition elements that simplify the manufacturing process by providing a regular, easy-to-form geometry that does not require complex stepped patterning. They maintain manufacturing precision by providing well-defined geometric references while reducing device complexity by eliminating the need for complex etching patterns in the connection region.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10886288B2Vertical semiconductor memory device structures including vertical channel structures and vertical dummy structures
Publication Date: 2021.01.05 SAMSUNG ELECTRONICS CO LTD
  • US10886288B2 patent drawing
  • US10886288B2 patent drawing
  • US10886288B2 patent drawing

AI summary

A vertical memory device structure can include a vertical channel structure that vertically penetrates through an upper structure and a lower structure of a stack structure in a cell array region of the device. The vertical channel structure can have a side wall with a stepped profile at a level in the vertical channel structure where the upper structure meets the lower structure. A vertical dummy structure can vertically penetrate through a staircase structure that is defined by the upper structure and the lower structure in a connection region of the device, and the vertical dummy structure can have a side wall with a planar profile at the level where the upper structure meets the lower structure.