Vertical Memory Arrays Using Stacked Semiconductor Wires
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Solution Overview
Problem
The challenge in integrated memory arrays is to increase memory density while maintaining compatibility with existing fabrication technologies, as existing memory arrays are difficult to scale down further.
Innovation Solution
The development of vertical memory designs using field effect transistor (FET) switching devices and semiconductor material wires, where data storage structures are formed at the ends of the wires, allowing for high-density memory unit cells to be vertically stacked, compatible with existing fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar memory arrays are used, then fabrication is easier, but integration density cannot be increased further
Solution Approach 1:
The patent transitions from conventional planar (2D) memory array architecture to a vertical (3D) architecture where memory unit cells are stacked vertically. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate rather than only the horizontal plane, allowing multiple layers of memory cells to be formed in the same footprint area.
Solution Approach 2:
The memory array is segmented into multiple discrete memory unit cells stacked vertically, with each unit cell comprising distinct functional components (semiconductor wire, gate structure, data storage structure) that can be independently formed and controlled. This segmentation allows for modular fabrication and addressing of individual memory cells within the vertical stack.
2Quantity of substance
If feature size is reduced to increase density, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the scaling parameter from lateral dimension reduction to vertical dimension utilization. Instead of continuously shrinking feature sizes in the planar direction, the invention maintains larger, more manufacturable feature sizes while achieving density improvement through vertical stacking. This parameter change allows fabrication processes to operate at more relaxed precision thresholds.
Solution Approach 2:
By moving the density improvement strategy from lateral scaling to vertical stacking, the patent avoids the diminishing returns and precision requirements associated with further lateral feature size reduction. The vertical dimension provides a new scaling pathway that is less constrained by current manufacturing precision capabilities.
3Quantity of substance
If vertical memory design is implemented, then integration density increases, but device complexity increases
Solution Approach 1:
The patent employs universal fabrication processes and materials that are compatible with existing semiconductor manufacturing techniques. The vertical memory structure uses standard semiconductor wires, gate dielectric materials, and conductive materials that can be deposited and patterned using established processes, thereby reducing the complexity increment despite the architectural change.
Solution Approach 2:
The fabrication process performs preliminary actions by first forming the semiconductor wires and gate structures in the vertical stack before adding the data storage structures. This sequencing simplifies the overall fabrication complexity by establishing the vertical architecture framework early, allowing subsequent steps to build upon this foundation using standard processes.
Data Source
AI summary
Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.