Vertical Semiconductor Memory Stacking for Integration Density
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Solution Overview
Problem
The challenge in semiconductor devices is to enhance integration density and reliability while maintaining efficient data processing capabilities, particularly in vertical transistor structures where existing designs face limitations in integration density and reliability.
Innovation Solution
A semiconductor device design featuring a stacked vertical structure with memory cell arrays, conductive layers, and bonding pads that allow for improved electrical connections and increased integration density, utilizing a base layer with gate electrodes and channels, and conductive layers for enhanced data storage and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar transistor structure is used, then the device structure is simple and easy to manufacture, but the integration density is low
Solution Approach 1:
The patent transitions from a planar (2D) transistor structure to a vertical (3D) transistor structure by stacking gate electrodes and channels in the vertical direction. This dimensional change allows multiple memory cell structures to be stacked above each other, significantly increasing integration density while maintaining manufacturability through established vertical stacking processes
2Quantity of substance
If integration density is increased through vertical stacking, then more memory cells can be packed, but reliability of electrical connections becomes more difficult to maintain
Solution Approach 1:
The patent divides the vertical stack into multiple discrete memory cell structures, each with its own gate electrodes and channels. This segmentation allows for modular construction where each stacked unit can be independently formed and connected, improving reliability by isolating potential failure points and enabling systematic quality control across multiple stacking layers
Solution Approach 2:
The patent implements a nested structure where bit lines are positioned between first and second memory cell structures, with channels penetrating through multiple gate electrode layers. This nested arrangement creates redundant connection paths and ensures that electrical connections remain reliable even as the vertical stack height increases, by embedding connection points within the stacked structure rather than at the extremes
Data Source
AI summary
A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.