Vertical Memory Devices Stair Structure Mold Area
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Solution Overview
Problem
The integration degree of VNAND flash memory devices decreases as the number of steps in the mold increases, due to the area expansion of the mold during the manufacturing process, which affects the performance and efficiency of the memory device.
Innovation Solution
A vertical memory device design with a substrate having a cell array region and a staircase region, where gate electrodes are spaced apart in specific directions, forming stair structures with varying step lengths to optimize the mold structure and reduce area expansion, and using insulating materials between the stair structures to maintain integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of steps in the mold is increased, then the integration degree of the VNAND flash memory device is improved, but the area of the mold increases
Solution Approach 1:
The patent transitions from a planar mold structure to a three-dimensional stair-structured mold. By stacking multiple steps vertically, the mold achieves higher integration degree without proportionally increasing the footprint area. The stair structure allows light to be reflected and focused through multiple levels, enabling complex patterning within a compact area.
Solution Approach 2:
The mold structure implements a nested configuration where multiple steps are stacked vertically within a compact footprint. Each step contains functional elements that contribute to the overall patterning process, allowing the mold to perform multiple functions within a reduced area. The steps are arranged concentrically and vertically to maximize space utilization.
2Productivity
If the number of steps in the mold is increased, then the integration degree of the VNAND flash memory device is improved, but the manufacturing complexity increases
Solution Approach 1:
The mold is divided into multiple discrete steps, each performing a specific function in the patterning process. This segmentation allows for modular design and fabrication, where each step can be independently optimized and manufactured. The stepped structure breaks down the complex patterning task into manageable segments that can be processed sequentially.
Solution Approach 2:
The patent employs asymmetric step configurations where different steps have different dimensions, orientations, and functional characteristics. This asymmetry allows each step to be optimized for its specific role in the patterning process, enabling higher integration degree while managing complexity through functional specialization rather than uniform repetition.
Data Source
AI summary
A vertical memory device includes a substrate having a cell array region and a staircase region. Gate electrodes are spaced apart from each other in first and third directions. A channel extends through the gate electrodes in the first direction on the cell array region. Each of the gate electrodes extends in a second direction. End portions in the second direction of one or more of the gate electrodes form a first stair structure on the staircase region of the substrate. The first stair structure includes first steps, a second step, and a third step sequentially disposed in the third direction. Each of the first steps has a first length, the second step has a second length greater than the first length, and the third step has a third length greater than the second length.