Vertical Memory Gate Contacts With Spacer-Isolated Staircase Plugs
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Solution Overview
Problem
In VNAND flash memory devices, the varying heights of gate electrode upper surfaces complicate the formation of contact plugs, leading to potential electrical shorts between gate electrodes due to the need to etch through multiple gate electrodes of different heights during contact plug formation.
Innovation Solution
A vertical memory device design featuring gate electrodes stacked in a staircase arrangement with spacers and burying patterns to electrically insulate contact plugs from adjacent gate electrodes, ensuring each contact plug connects only to its intended gate electrode while avoiding electrical shorts from underlying electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If openings for forming contact plugs are formed to contact upper surfaces of gate electrodes, then electrical connection between contact plugs and gate electrodes is achieved, but electrical shorts between gate electrodes occur due to varying heights of gate electrode upper surfaces
Solution Approach 1:
The patent introduces spacers as intermediary insulating structures positioned between the contact plug and adjacent gate electrodes. These spacers act as mediators that prevent direct electrical contact between the conductive contact plug and neighboring gate electrodes, thereby eliminating the harmful electrical short while maintaining the necessary electrical connection to the target gate electrode.
Solution Approach 2:
The patent extracts the problematic varying heights of gate electrode upper surfaces by introducing a planarization layer that creates a uniform surface level. This extraction of the height variation problem allows contact plugs to be formed at a consistent depth without penetrating into underlying gate electrodes, thereby preventing electrical shorts while maintaining reliable electrical connections.
2Reliability
If contact plugs extend through multiple gate electrodes of different heights, then connection to the target gate electrode is achieved, but manufacturing complexity increases due to precise depth control requirements
Solution Approach 1:
The patent applies preliminary planarization by forming a planarization layer over the gate electrodes before creating the contact plugs. This preliminary action creates a uniform surface that simplifies subsequent contact plug formation, eliminating the need for precise depth control through varying height gate electrodes and significantly reducing manufacturing complexity.
Solution Approach 2:
The spacers serve as intermediaries that define the stopping depth for contact plug formation. By positioning spacers at the desired contact depth, the manufacturing process can stop precisely at the spacer level without requiring complex control mechanisms to navigate the varying heights of underlying gate electrodes.
3Productivity
If gate electrodes are stacked in a staircase arrangement, then vertical memory device structure is achieved, but contact plug formation becomes more difficult due to height variations
Solution Approach 1:
The patent applies preliminary planarization by forming a planarization layer that covers the staircase arrangement of gate electrodes, creating a uniform surface level. This preliminary action maintains the high integration density benefits of the staircase structure while simplifying contact plug formation by eliminating the need to navigate varying heights during the contact formation process.
Solution Approach 2:
The patent resolves the height variation problem by transitioning to another dimension - using spacers that extend vertically from the planarized surface to define contact depths. This dimensional approach allows the contact plug formation process to proceed on a uniform surface while the spacers provide the necessary depth control in the vertical dimension, maintaining both productivity and ease of manufacture.
Data Source
AI summary
A vertical memory device including gate electrodes on a substrate, the gate electrodes being spaced apart in a first direction and stacked in a staircase arrangement; a channel extending through the gate electrodes in the first direction; a first contact plug extending through a pad of a first gate electrode to contact an upper surface of the first gate electrode, the first contact plug extending through a portion of a second gate electrode, and the second gate electrode being adjacent to the first gate electrode; a first spacer between the first contact plug and sidewalls of the first gate electrode and the second gate electrode facing the first contact plug, the first spacer electrically insulating the first contact plug from the second gate electrode; and a first burying pattern contacting bottom surfaces of the first contact plug and the first spacer, the first burying pattern including an insulating material.