Vertical Memory Devices Staircase Structure Dummy Gate Electrodes
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Solution Overview
Problem
The manufacturing process of VNAND flash memory devices is inefficient due to the repetitive etching and trimming processes required to form staircase structures, which increase process time and cost as the number of steps in the staircase structure increases.
Innovation Solution
A vertical memory device design that includes a substrate with a cell array region and an extension region, featuring gate electrodes stacked in a perpendicular direction with pads forming a staircase structure, and dummy gate electrodes spaced apart to reduce the need for repetitive etching and trimming processes, thereby optimizing the manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of steps in the staircase structure increases to enhance device functionality, then the device complexity and integration degree improve, but the photoresist pattern thickness increases and the number of repetitive trimming processes increases, leading to increased process time and manufacturing cost
Solution Approach 1:
The patent introduces dummy gate electrodes in advance during the formation stage, which pre-establish the geometric reference framework needed for subsequent etching processes. This preliminary structural preparation eliminates the need for multiple iterative trimming operations, as the real gate electrodes can be directly formed with correct dimensions using the dummy structures as masks and references.
Solution Approach 2:
The dummy gate electrodes serve as intermediary structures that mediate between the staircase mold geometry and the final real gate electrode formation. These intermediary elements provide the necessary geometric control and dimensional reference without being part of the final functional device, thus simplifying the overall manufacturing process.
2Device complexity
If the number of steps in the staircase structure increases to enhance device functionality, then the device complexity and integration degree improve, but the photoresist pattern thickness increases and the number of repetitive trimming processes increases, leading to increased manufacturing cost
Solution Approach 1:
The dummy gate electrodes are formed in advance as part of the initial structure fabrication, establishing a permanent geometric reference that eliminates the need for costly repetitive photoresist trimming operations. This preliminary action converts a multi-step costly process into a simpler, more cost-effective manufacturing approach.
Solution Approach 2:
The dummy gate electrodes act as physical copies or templates that replicate the desired geometric relationships and dimensional proportions. By using these copied structures as etching masks and references, the manufacturing process achieves high precision without requiring multiple expensive trimming iterations.
3Productivity
If dummy gate electrodes are added to reduce etching and trimming processes, then the manufacturing efficiency improves and process time decreases, but the device structure becomes more complex during fabrication
Solution Approach 1:
The dummy gate electrodes are temporarily introduced during fabrication to enable simplified processing, then selectively removed or discarded in later stages. These sacrificial structures serve their purpose during critical fabrication steps and are subsequently eliminated, leaving only the simplified real gate electrode structure in the final device.
Solution Approach 2:
The dummy gate electrodes are extracted or separated from the final functional device structure. They are used as temporary auxiliary elements during manufacturing but are not part of the ultimate product, thus adding fabrication complexity only temporarily while delivering permanent manufacturing efficiency gains.
Data Source
AI summary
A vertical memory device, including: a substrate including a cell array region and an extension region; gate electrodes stacked on each other with a plurality of levels, wherein each of the gate electrodes includes a pad, and wherein the pads disposed on the gate electrodes form at least one staircase structure on the extension region of the substrate; a channel extending in a first direction on the cell array region of the substrate through at least one of the gate electrodes; and dummy gate electrode groups disposed on the extension region of the substrate, wherein the dummy gate electrode groups includes dummy gate electrodes, wherein each of the dummy gate electrodes are spaced apart from a corresponding gate electrode among the gate electrodes stacked at a same level, wherein the dummy gate electrode groups are spaced apart from each other in a second direction.