Vertical Semiconductor Memory With Stepped Gate Stacks
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Solution Overview
Problem
The existing two-dimensional semiconductor memory devices face limitations in degree of integration due to high equipment costs and limited chip die area, necessitating the development of vertical-type semiconductor memory devices with improved reliability and economic feasibility.
Innovation Solution
A vertical-type semiconductor memory device is designed with a substrate having gate stack structures with stepped top surfaces, conductive lines with linear segments extending in different directions, and common source lines formed to match the shape of the gate stack structures, enhancing integration and manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional semiconductor memory devices are used to increase degree of integration, then manufacturing cost increases due to high-priced equipment and limited chip die area, but vertical-type devices offer improved integration without these constraints
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertical structures by stacking gate electrodes and insulating layers vertically. This dimensional change enables higher integration density without requiring additional chip area or expensive fine-pattern equipment, as the storage capacity increases through the vertical stacking of multiple gate electrodes (e.g., first through sixth gate electrodes) and corresponding insulating layers within the same footprint.
2Productivity
If complex three-dimensional vertical structures are implemented to improve integration density, then device reliability may deteriorate due to potential structural collapse, but proper design ensures both high integration and reliability
Solution Approach 1:
The vertical structure is segmented into multiple discrete functional units: alternating layers of first through sixth gate electrodes and first through fifth insulating layers. Each gate electrode and insulating layer pair forms an independent structural unit that can be formed and controlled separately during manufacturing. This segmentation reduces the risk of overall structural collapse by distributing mechanical stresses across multiple discrete interfaces rather than relying on a single complex monolithic structure.
Solution Approach 2:
Different regions of the vertical structure are assigned different functional qualities: gate electrodes in specific regions serve as control gates, string select gates, or ground select gates, while insulating layers provide electrical isolation in corresponding regions. This local differentiation of functionality allows each part of the vertical stack to be optimized for its specific role, ensuring structural integrity while achieving high integration density through specialized regional functions rather than uniform structure throughout.
Data Source
AI summary
A semiconductor device including: a substrate including a top surface configured to extend in a first direction and a second direction that are perpendicular to each other; gate stack structures disposed on the substrate, spaced apart from one another in the first direction and configured to extend in the second direction; a first region in which levels of top surfaces of the gate stack structures are constant; a second region in which levels of top surfaces of the gate stack structures are stepped, the second region configured to surround at least a portion of the first region; and conductive lines disposed in the second region between the gate stack structures and configured to extend in the second direction in an uneven form.