Vertical Memory Device Stepped Substrate Leakage Control
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Solution Overview
Problem
The challenge in the development of vertical-type memory devices is to enhance their reliability while maintaining high integration and capacity, particularly in the context of increasing data processing demands in smaller electronic products.
Innovation Solution
The proposed solution involves a vertical-type memory device design with a substrate having a cell array region and a connection region, featuring stacked gate electrode layers, channel structures, and dummy channel structures. The substrate has a stepped structure in the connection region, with channel structures having a greater vertical length than dummy channel structures, and epitaxial layers in contact with the substrate, which supports improved reliability and leakage current characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically to increase integration degree, then storage capacity is improved, but device reliability deteriorates due to increased leakage current and structural complexity
Solution Approach 1:
The connection region is divided into multiple levels corresponding to different gate electrode layers, with dummy channel structures segmented by depth. First dummy channel structures are formed at a first depth to connect to first gate electrode layers, while second dummy channel structures are formed at a second depth to connect to second gate electrode layers. This segmentation allows targeted leakage current control at different vertical levels, improving reliability while maintaining high storage capacity through vertical stacking.
Solution Approach 2:
Different types of dummy channel structures are selectively placed at different depths in the connection region. First dummy channel structures are positioned to address leakage issues at upper levels, while second dummy channel structures address leakage at lower levels. This local differentiation of dummy channel structures enables precise control of leakage current in specific regions, enhancing overall device reliability without compromising the vertical stacking architecture.
2Adaptability or versatility
If gate electrode layers are extended into the connection region to form stacked structures, then connectivity is improved, but manufacturing complexity increases due to stepped structures
Solution Approach 1:
The connection region utilizes the vertical dimension by forming dummy channel structures at multiple depths corresponding to different gate electrode layers. First dummy channel structures are formed at a first depth while second dummy channel structures are formed at a second depth, creating a three-dimensional stacked connection architecture. This vertical dimensionality enables enhanced connectivity between memory cells and peripheral circuits while the systematic formation process manages manufacturing complexity.
Solution Approach 2:
Dummy channel structures are formed in advance during the manufacturing process, with first dummy channel structures formed at a first depth and second dummy channel structures formed at a second depth before final device operation. This preliminary formation of depth-separated dummy channel structures establishes the stacked connection architecture early in manufacturing, simplifying subsequent processing steps and reducing overall manufacturing complexity.
3Productivity
If channel structures are made longer vertically to increase storage density, then integration is improved, but leakage current increases reducing reliability
Solution Approach 1:
Dummy channel structures are introduced as intermediary elements in the connection region to control leakage current. These dummy channel structures are positioned at different depths and selectively connected to different gate electrode layers, acting as mediators that regulate charge flow and suppress leakage current in the vertical channel structures, thereby maintaining high integration density while improving reliability.
Solution Approach 2:
The potential harmful effect of increased leakage current in long vertical channel structures is converted into a benefit by introducing dummy channel structures at specific depths. These dummy structures, when selectively connected to appropriate gate electrode layers, transform the leakage problem into an opportunity for controlled charge management, improving reliability while maintaining the high integration advantages of vertical channel structures.
Data Source
AI summary
A vertical-type memory device a vertical-type memory device comprising a substrate including a first region and a second region, adjacent to the first region, a first conductive layer extending on the first region and the second region, and a second conductive layer extending on the first region and the second region, the second conductive layer stacked on the first conductive layer. An upper surface of the substrate has a step portion at a boundary between the first region and the second region, and the upper surface of the substrate in the first region is lower than in the second region.