Vertical Memory Mold Layout for Scribe Lane Stress Balance
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Solution Overview
Problem
In the manufacturing of VNAND flash memory devices, the etching process for patterning the mold layer can lead to stress differences between the chip region and the scribe lane region, affecting the accuracy of tests and potentially the device's performance.
Innovation Solution
The method involves alternately and repeatedly stacking insulation and sacrificial layers to form a mold layer on a substrate, with a portion of the mold layer on the scribe lane region not being removed, thus maintaining the stress balance similar to the chip region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the etching process is performed to pattern the mold layer into a staircase shape, then the mold layer can be formed with multiple levels, but stress differences occur between the chip region and the scribe lane region
Solution Approach 1:
The patent applies local quality by making different parts of the mold layer have different properties: the chip region undergoes complete etching to form staircase structures, while the scribe lane region retains the full-thickness mold layer. This localized differentiation allows precise patterning where needed while maintaining stress balance in regions where complete removal would cause instability.
Solution Approach 2:
The patent segments the substrate into distinct regions (chip region and scribe lane region) with different mold layer configurations. The chip region is divided into multiple levels through selective etching, while the scribe lane region maintains a unified structure, allowing independent optimization of each segment's properties.
2Quantity of substance
If the number of levels of the mold layer is increased, then the storage capacity is improved, but the thickness of the insulating interlayer must be increased which complicates the manufacturing process
Solution Approach 1:
The patent transitions from a planar (2D) structure to a vertical (3D) stacked structure by forming multiple levels of mold layers and insulating interlayers in the thickness direction. This dimensional change allows increased storage capacity without expanding the chip area, effectively utilizing the vertical space for additional memory cells.
Data Source
AI summary
A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.